mpc92469 Integrated Device Technology, mpc92469 Datasheet

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mpc92469

Manufacturer Part Number
mpc92469
Description
400 Mhz Low Voltage Pecl Clock Synthesizer W/spread Spectrum
Manufacturer
Integrated Device Technology
Datasheet

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Part Number:
mpc92469AC
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
mpc92469ACR2
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT™ / ICS™ PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM
400 MHz Low Voltage PECL
Clock Synthesizer w/Spread
Spectrum
for high performance clock generation in mid-range to high-performance tele-
com, networking and computing applications. With output frequencies from
25 MHz to 400 MHz and the support of differential PECL output signals the
device meets the needs of the most demanding clock applications.
Features
Functional Description
internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 400
to 800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator
frequency f
by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase
lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (400 to 800 MHz). The M-value
must be programmed by the serial or parallel interface.
ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven
differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 Ω to V
positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize
noise induced jitter.
inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes
valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control
inputs from floating.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See
MING INTERFACE
bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
The MPC92469 is a 3.3 V compatible, PLL based clock synthesizer targeted
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 2⋅M times the reference frequency
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]
The serial interface centers on a eighteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
25 MHz to 400 MHz synthesized clock output signal
Spread Spectrum output for EMI reduction
32-lead Pb-free package available
Differential PECL output
LVCMOS compatible control inputs
On-chip crystal oscillator for reference frequency generation
3.3 V power supply
Fully integrated PLL
Minimal frequency overshoot
Serial 3-wire programming interface
Parallel programming interface for power-up
32-lead LQFP packaging
SiGe Technology
Ambient temperature range 0°C to +70°C
Pin compatible to the MC12429, MPC9229, MPC92429, and ICS84329
XTAL
, the PLL feedback-divider M and the PLL post-divider N determine the output frequency.
for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0]
1
400 MHz LOW VOLTAGE
w/SPREAD SPECTRUM
32-LEAD LQFP PACKAGE
32-LEAD LQFP PACKAGE
CLOCK SYNTHESIZER
Pb-FREE PACKAGE
MPC92469REV 4 JANUARY 23, 2007
CASE 873A-03
CASE 873A-03
FA SUFFIX
AC SUFFIX
CC
MPC92469
– 2.0 V. The
PROGRAM-

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mpc92469 Summary of contents

Page 1

... MHz Low Voltage PECL Clock Synthesizer w/Spread Spectrum The MPC92469 is a 3.3 V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance tele- com, networking and computing applications. With output frequencies from 25 MHz to 400 MHz and the support of differential PECL output signals the device meets the needs of the most demanding clock applications ...

Page 2

... SHIFT REGISTER Figure 1. MPC92469 Logic Diagram MPC92469 Figure 2. MPC92469 32-Lead Package Pinout (Top View FOUT OE 10 FOUT 11 SYNC TEST TEST 3 2 T-LATCH SSM-LATCH 0 BITS 4-6 BITS 0 M[3] 14 M[2] 13 ...

Page 3

... PLL positive power supply (analog power supply). CC Output Division Function output low stops F in the logic low state OUT pins must be connected to the CC Output Frequency Range 200 – 400 MHz 100 – 200 MHz 50 – 100 MHz 25 – 50 MHz MPC92469REV 4 JANUARY 23, 2007 ...

Page 4

... Maximum Supply Current CC 1. Inputs have pull-down resistors affecting the input current. 2. Outputs terminated 50 Ω The MPC92469 TEST output levels are compatible to the MC12429 output levels. IDT™ / ICS™ PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM Min 200 2000 200 ...

Page 5

... MHz 200 MHz 100 MHz 50 MHz 0.3 ns 20% to 80% 10 MHz ≠ ≠ kHz MHz XTAL ±0.30 ±0 300 MHz out -0.3 -0 MHz XTAL x M ÷ VCO XTAL MPC92469REV 4 JANUARY 23, 2007 ...

Page 6

... M is the PLL feedback- XTAL divider and N is the PLL post-divider. The input frequency and the selection of the feedback divider M is limited by the VCO-frequency range. f and M must be configured to XTAL Table 7. MPC92469 Frequency Operating Range VCO frequency for a crystal interface frequency of M M[8: 160 ...

Page 7

... MPC92469 itself. However the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110 the MPC92469 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives ...

Page 8

... Figure 4. Down Spread % across VCO Range with 16 MHz Reference Figure 5. Center Spread % across VCO Range with 16 MHz Reference IDT™ / ICS™ PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM SS2 SS1 SS0 Figure 3. Serial Interface Timing Diagram Last Bit MPC92469REV 4 JANUARY 23, 2007 ...

Page 9

... IDT™ / ICS™ PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM filter on the V illustrates a typical power supply filter scheme. The MPC92469 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs ...

Page 10

... XTAL_IN and XTAL_OUT pins to ground may be used to trim the frequency as shown in Figure 8. The crystal and optional trim capacitors should be located as close to the MPC92469 XTAL_IN and XTAL_OUT pins as possible to avoid any board level parasitic. Table 12. Recommended Crystal Specifications Parameter ...

Page 11

... ˚ MPC92469REV 4 JANUARY 23, 2007 ...

Page 12

... MPC92469 400MHZ, LOW VOLTAGE, PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 netcom@idt.com 408-284-8200 480-763-2056 Fax: 408-284-2775 Corporate Headquarters Asia Pacific and Japan Integrated Device Technology, Inc. Integrated Device Technology 6024 Silver Creek Valley Road Singapore (1997) Pte ...

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