sy89837u Micrel Semiconductor, sy89837u Datasheet - Page 4

• Manufacturer Part Number: sy89837u
• Description: Sy89837u Precision 1 8 Lvpecl Fanout Buffer With 2 1 Runt Pulse Eliminator Input Mux
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
RPE MUX and Fail-Safe Input
applications where switching from one clock to another clock
without runt pulses (short cycles) is required. It features two
unique circuits:
1. Runt-Pulse Eliminator (RPE) Circuit
two clocks and prevents any runt pulses from occurring
during the switchover transition. The design of both clock
inputs is identical (i.e., the switchover sequence and
protection is symmetrical for both input pair, IN0 or IN1.
Thus, either input pair may be defined as the primary input).
If not required, the RPE function can be permanently
disabled to allow the switchover between inputs to occur
immediately. For more detail on how to disable the RPE
function within the MUX, see the “Power-On Reset (POR)”
section.
2. Fail-Safe Input (FSI) Circuit
input pair that drops below the minimum amplitude
requirement. If the selected input pair drops sufficiently below
the 200mV minimum single-ended input amplitude limit (V
or 400mV differentially (Vdiff_IN), the output will latch to the
last valid clock state.
M9999-022007
[e-mail] or [phone]
The SY89837U is optimized for clock switchover
The RPE MUX provides a “glitchless” switchover between
The FSI function provides protection against a selected
DETAILED FUNCTIONAL DESCRIPTION
OUTPUT
CLK1
CLK2
SEL
Runt pulse eliminated
from output
Select CLK1
3 to 5 falling edges
Figure 2. Timing Diagram 1
of CLK1
Stage 1
IN
),
4
RPE and FSI Functionality
is described with the following four case descriptions. All
descriptions are related to the true inputs and outputs. The
primary (or selected) clock is called CLK1, the secondary
(or alternate) clock is called CLK2. Due to the totally
asynchronous relation of the IN and SEL signals and an
additional internal protection against metastability, the
number of pulses required for the operations described in
cases 1 through 4 can vary within certain limits. Refer to
“Timing Diagrams” and “Applications” section for detailed
information.
Case #1 Two Normal Clocks and RPE Enabled.
running clocks IN0 and IN1 must not be greater than 1.5:1.
For example, if the IN0 clock is 500MHz, the IN1 clock
must be within the range of 334MHz to 750MHz.
clock, the switchover from CLK1 to CLK2 will occur in three
stages:
4 to 5 falling edges
The basic operation of the RPE MUX and FSI functionality
In this case the frequency difference between the two
If the SEL input changes state to select the alternate
• Stage 1: The output will continue to follow CLK1
• Stage 2: The output will remain LOW for a
• Stage 3: The output follows CLK2.
Select CLK2
of CLK2
for a limited number of pulses.
limited number of pulses of CLK2.
Stage 2
Stage 3
Precision Edge
SY89837U
®