sy89200u Micrel Semiconductor, sy89200u Datasheet - Page 3

• Manufacturer Part Number: sy89200u
• Description: Sy89200u Ultra-precision 1 8 Lvds Fanout With Three ?1/?2/?4 Clock Divider Output Banks
• Manufacturer: Micrel Semiconductor

Pin Description
Truth Table
Micrel, Inc.
August 2007
Notes:
1. /MR asynchronously forces Q0 – Q7 LOW (/Q0 – /Q7 HIGH).
2. EN forces Q0 – Q7 LOW between 2 and 6 input clock cycles after the falling edge of EN. Refer to “Timing Diagram” section.
3. EN synchronously enables the outputs between two and six input clock cycles after the rising edge of EN. Refer to “Timing Diagram” section.
10, 19, 22, 31
Pin Number
30, 29, 28,
27, 26, 25,
16, 15, 14,
13, 12, 11
/MR
1, 20, 21
24, 23
18, 17
0
1
1
1
3, 6
32
2
7
8
4
5
9
(1)
EN
Q0, /Q0, /Q1,
/Q1, Q2, /Q2
Q4, /Q4, Q5,
/Q5, Q6, /Q6
Pin Name
VREF-AC
DIVSEL1
DIVSEL2
DIVSEL3
X
0
1
1
Exposed
Q3, /Q3
Q7, /Q7
(2,3)
IN, /IN
GND
VCC
/MR
VT
EN
DIVSEL1
Pin Function
Differential Input: This input pair is the differential signal input to the device. This input
accepts AC- or DC-coupled signals as small as 100mV. The input pair internally
terminates to a VT pin through 50Ω. Note that these inputs will default to an indeterminate
state if left open. Please refer to the “Input Interface Applications” section for more details.
Single-Ended Inputs: These TTL/CMOS inputs select the device ratio for each of the
three banks of outputs. Note that each of these inputs is internally connected to a 25kΩ
pull-up resistor and will default to logic HIGH state if left open. The input-switching
threshold is V
Input Termination Center-Tap: Each side of the differential input pair terminates to the VT
pin. The VT pin provides a center-tap to a termination network for maximum interface
flexibility. See “Input Interface Applications” section for more details.
Reference Voltage: This output biases to V
and /IN. For AC-coupled applications, connect VREF-AC directly to the VT pin. Bypass
with 0.01µF low ESR capacitor to V
Single-Ended Input: This TTL/CMOS input disable and enable the Q0 – Q7 outputs. This
input is internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state
if left open. The input-switching threshold is V
functional description, refer to Figures 2a through 2c.
Bank 1 LVDS differential output pairs controlled by DIVSEL1: LOW Q0 – Q3 = ÷1 HIGH,
Q0 – Q3 = ÷2. Unused output pairs should be terminated with 100Ω across the differential
pair.
Bank 2 LVDS differential output pairs controlled by DIVSEL2: LOW Q4 – Q6 = ÷2 HIGH,
Q4 – Q6 = ÷2. Unused output pairs should be terminated with 100Ω across the differential
pair.
Bank 3 LVDS differential output pairs controlled by DIVSEL3: LOW Q7 = ÷2 HIGH. Q7 =
÷2. Unused output pairs should be terminated with 100Ω across the differential pair.
Single-Ended Input: This TTL/CMOS-compatible master reset function asynchronously
sets Q0 – Q7 outputs LOW, /Q0 – /Q7 outputs HIGH, and holds them in that state as long
as /MR remains LOW. This input is internally connected to a 25kΩ pull-up resistor and will
default to a logic HIGH state if left open. The input-switching threshold is V
Positive power supply. Bypass with 0.1µF||0.01µF low ESR capacitors.
Ground and exposed pad must be connected to the same GND plane on the board.
X
X
0
1
DIVSEL2
CC
/2.
X
X
0
1
3
DIVSEL3
X
X
0
1
CC
. Maximum sink/source capability is 0.5mA.
CC
CC
-1.2V. It is used for AC-coupling inputs IN
Q0 – Q3
/2. For the input enable and disable
[e-mail]
÷1
÷2
0
0
Q4 – Q6
÷2
÷4
0
0
or [phone]
M9999-082407-E
CC
/2.
SY89200U
Q7
÷2
÷4
0
0