sy89228u Micrel Semiconductor, sy89228u Datasheet - Page 7

• Manufacturer Part Number: sy89228u
• Description: Sy89228u 1ghz Precision, Lvpecl ? 3, ? 5 Clock Divider With Fail-safe Input And Internal Termination
• Manufacturer: Micrel Semiconductor

Functional Description
Fail-Safe Input (FSI)
The input includes a special failsafe circuit to sense
the amplitude of the input signal and to latch the
outputs when there is no input signal present, or when
the amplitude of the input signal drops sufficiently
below
Maximum frequency of the SY89228U is limited by the
FSI function. Refer to Figure 1b.
Input Clock Failure Case
If the input clock fails to a floating, static, or extremely
low signal swing, the FSI function will eliminate a
metastable condition and guarantee a stable output
signal. No ringing and no undetermined state will
occur at the output under these conditions.
Note that the FSI function will not prevent duty cycle
distortion in case of a slowly deteriorating (but still
toggling) input signal as it nears the FSI threshold
(typically, 30mV). Due to the FSI function, the
propagation delay will depend on rise and fall time of
the input signal and on its amplitude. See “Typical
Operating Characteristics” for detailed information.
Output Duty Cycle Equation
For a non 50% input, derate the spec by:
For Divide by 3:
For Divide by 5:
X = input Duty Cycle, in %
Example: if a 45% input duty cycle is applied or X=45,
in divide by 3 mode, the spec would expand by 1.67%
to 44.3%-55.7%
August 2007
(0.5 -
(0.5 -
100mV
1
2
+
+
PK
3
100
5
100
X
X
(200mV
) x100, in %
) x100, in %
PP
),
typically
30mV
PK
.
7
Enable (EN)
EN is a synchronous TTL/CMOS-compatible input that
enables/disables the outputs based on the input to
this pin. Internal 25kΩ pull-up resistor defaults the
input to logic HIGH if left open. Input switching
threshold is V
The Enable function operates as follows:
Refer to Figure 1c for examples.
Divider Operation
The divider operation uses both the rising and falling
edge of the input clock. For divide by 3, the falling
edge of the second input clock cycle will determine
the falling edge of the output. For divide by 5, the
falling edge of the third input clock cycle. Refer to
Figure 1d.
1. The
2. The
synchronous so that the clock outputs will
be enabled or disabled following a rising
and a falling edge of the input clock when
switching from EN = LOW to EN = HIGH.
However, when switching from EN = HIGH
to EN = LOW, the clock outputs will be
disabled following an input clock rising
edge and an output clock falling edge.
guarantees the full pulse width at the
output before the clock outputs are
disabled, non-depending on the divider
ratio.
CC
enable/disable
/2.
[e-mail]
enable/disable
function
or [phone]
function
M9999-080707-A
always
is