lmx2377u National Semiconductor Corporation, lmx2377u Datasheet - Page 31

• Manufacturer Part Number: lmx2377u
• Description: Lmx2377u Pllatinum? Ultra Low Power Dual Frequency Synthesizer For Rf Personal Communications 2.5 Ghz/1.2 Ghz
• Manufacturer: National Semiconductor Corporation

1.0 Functional Description
The basic phase-lock-loop (PLL) configuration consists of a
high-stability crystal reference oscillator, a frequency synthe-
sizer such as the National Semiconductor LMX2377U, a
voltage controlled oscillator (VCO), and a passive loop filter.
The frequency synthesizer includes a phase detector, cur-
rent mode charge pump, programmable reference R and
feedback N frequency dividers. The VCO frequency is es-
tablished by dividing the crystal reference signal down via
the reference divider to obtain a comparison reference fre-
quency. This reference signal, F
input of a phase/frequency detector and compared with the
feedback signal, F
frequency down by way of the feedback divider. The
phase/frequency detector measures the phase error be-
tween the F
are directly proportional to the phase error. The charge pump
then pumps charge into or out of the loop filter based on the
magnitude and direction of the phase error. The loop filter
converts the charge into a stable control voltage for the
VCO. The phase/frequency detector’s function is to adjust
the voltage presented to the VCO until the feedback signal’s
frequency and phase match that of the reference signal.
When this “Phase-Locked” condition exists, the VCO fre-
quency will be N times that of the comparison frequency,
where N is the feedback divider ratio.
1.1 REFERENCE OSCILLATOR INPUT
The reference oscillator frequency for both the Main and Aux
PLLs is provided from an external reference via the OSC
pin. The reference buffer circuit supports input frequencies
from 2 to 40 MHz with a minimum input sensitivity of 0.5 V
The reference buffer circuit has an approximate V
threshold and can be driven from an external CMOS or TTL
logic gate. Typically, the OSC
of a crystal oscillator.
1.2 REFERENCE DIVIDERS (R COUNTERS)
The reference dividers divide the reference input signal,
OSC
circuits feeds the reference input of the phase detector. This
reference input to the phase detector is often referred to as
the comparison frequency. The divide ratio should be chosen
such that the maximum phase comparison frequency (F
or F
The Main and Aux reference dividers are each comprised of
15-bit CMOS binary counters that support a continuous in-
teger divide ratio from 2 to 32767. The Main and Aux refer-
ence divider circuits are clocked by the output of the refer-
ence buffer circuit which is common to both.
1.3 PRESCALERS
The f
bipolar, differential-pair amplifier. The output of the bipolar,
differential-pair amplifier drives a chain of ECL D-type
φAux
in
IN
, by a factor of R. The output of the reference divider
) of 10 MHz is not exceeded.
Main and f
r
and F
p
, which was obtained by dividing the VCO
p
IN
signals and outputs control signals that
Main input pins drive the input of a
in
pin is connected to the output
r
, is then presented to the
CC
/2 input
φMain
PP
in
.
31
flip-flops in a dual modulus configuration. The output of the
prescaler is used to clock the subsequent feedback dividers.
The Main PLL complementary inputs can be driven differen-
tially, or the negative input can be AC coupled to ground
through an external capacitor for single ended configuration.
A 16/17 or a 32/33 prescale ratio can be selected for the
LMX2377U Main synthesizer. On the other hand, the Aux
PLL is only intended for single ended operation. An 8/9 or a
16/17 prescale ratio can be selected for the LMX2377U Aux
synthesizer.
1.4 PROGRAMMABLE FEEDBACK DIVIDERS (N
COUNTERS)
The programmable feedback dividers operate in concert with
the prescalers to divide the input signal f
The output of the programmable reference divider is pro-
vided to the feedback input of the phase detector circuit. The
divide ratio should be chosen such that the maximum phase
comparison frequency (F
exceeded.
The programmable feedback divider circuit is comprised of
an A counter (swallow counter) and a B counter (program-
mble binary counter). The Main N_CNTRA and the Aux
N_CNTRA counters are both 5-bit CMOS swallow counters,
programmable from 0 to 31. The Main N_CNTRB and Aux
N_CNTRB counters are both 13-bit CMOS binary counters,
programmable from 3 to 8191. A continuous integer divide
ratio is achieved if N ≥ P
prescaler selected. Divide ratios less than the minimum con-
tinuous divide ratio are achievable as long as the binary
programmable counter value is greater than the swallow
counter value (N_CNTRB ≥ N_CNTRA). Refer to Sections
2.5.1, 2.5.2, 2.7.1 and 2.7.2 for details on how to program
the N_CNTRA and N_CNTRB counters. The following equa-
tions are useful in determining and programming a particular
value of N:
N = (P x N_CNTRB) + N_CNTRA
f
Definitions:
IN
F
f
N_CNTRA: Main or Aux A counter value
N_CNTRB: Main or Aux B counter value
P:
IN
= N x F
φ
:
:
φ
Main or Aux phase detector comparison
frequency
Main or Aux input frequency
Preset
prescaler
Main synthesizer: P = 16 or 32
Aux synthesizer: P = 8 or 16
modulus
*
φMain
(P−1), where P is the value of the
or F
of
φAux
the
) of 10 MHz is not
IN
by a factor of N.
dual
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