lmx2532 National Semiconductor Corporation, lmx2532 Datasheet
lmx2532
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lmx2532 Summary of contents
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... LMX2522 and LMX2532 include an Integer-N IF PLL also. For more flexible loop filter designs, the IF PLL includes a 4-level programmable charge pump. Together with an exter- nal VCO and loop filter, LMX2522 and LMX2532 make a complete closed loop IF synthesizer system. Serial data is transferred to the device via a three-wire MICROWIRE interface (DATA, LE, CLK) ...
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Connection Diagram NOTE: Analog ground connected through exposed die attached pad. Pin Descriptions Pin Number ...
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... Ordering Information Part Number RF Min. (MHz) LMX2522LQX1635 1619.62 LMX2522LQ1635 1619.62 LMX2532LQX0967 954.42 LMX2532LQ0967 954.42 LMX2532LQX1065 1052.64 LMX2532LQ1065 1052.64 Part Number Description RF Max. RF Center IF GPS (MHz) (MHz) (MHz) (MHz) ~ 1635 1649.62 440.76 1355.04 ~ 1635 1649.62 440.76 1355.04 ~ 967 979.35 170.76 1490.04 ~ 967 979 ...
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... OB_CRL [1: OB_CRL [1: Lock Time (Note 7) LMX2522LQ1635 LMX2532LQ0967 LMX2532LQ1065 Reference Spurs RMS Phase Error RF PLL in all band L(f) Phase Noise LMX2522LQ1635 LMX2532LQ0967 LMX2532LQ1065 2nd Harmonic Suppression 3rd Harmonic Suppression www.national.com Recommended Operating (Notes 1, Conditions Parameter Ambient Temperature Supply Voltage (to GND) V Units Note 1: Absolute Maximum Ratings indicate limits beyond which damage to V the device may occur ...
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... Reference Spurs RMS Phase Error L(f) Phase Noise 2nd Harmonic Suppression 3rd Harmonic Suppression IF PLL f Operating Frequency LMX2522LQ1635 Fin (Note 8) LMX2532LQ0967 LMX2532LQ1065 p IF Input Sensitivity Fin f Phase Detector Frequency ΦIF I Charge Pump Current CPout DIGITAL INTERFACE (DATA, CLK, LE, LD, CE) V High-Level Input Voltage ...
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Electrical Characteristics Symbol Parameter MICROWIRE INTERFACE TIMING t Data to Clock Set Up Time CS t Data to Clock Hold Time CH t Clock Pulse Width High CWH t Clock Pulse Width Low CWL t Clock to Latch Enable Set ...
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... VCO RF_B: Preset divide ratio of binary 4-bit programmable counter (2 ≤ RF_B ≤ 15) RF_A: Preset divide ratio of binary 3-bit swallow counter (0 ≤ RF_A ≤ 7 for LMX2522 or 0 ≤ RF_A ≤ 5 for LMX2532) RF_FN: Preset numerator of binary 11-bit modulus counter < (0 ≤ RF_FN 1920 for f = 19.20 MHz or 0 ≤ ...
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... W1 W2 www.national.com POWER DOWN MODE (Continued) The LMX2522 and LMX2532 include a power down mode to reduce the power consumption. The LMX2522/32 enters into the power down mode either by taking the CE pin LOW or by IF_A f /IF_R OSC setting the power down bits in Register R1. Table 5 summa- (kHz) rizes the power down function ...
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Functional Description MICROWIRE INTERFACE The programmable register set is accessed via the MICROWIRE serial interface. The interface comprises three signal pins: CLK, DATA, and LE. Serial data (DATA) is clocked into the 24-bit shift register on the rising edge of ...
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Programming Description CONTROL REGISTER CONTENT MAP The serial interface has a 24-bit shift register to store the incoming data bits temporarily. The incoming Data is loaded into the shift register from MSB to LSB. The Data is shifted at the ...
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... The waveform of the lock detect mode is shown in Figure 1, in the Functional Description section on LOCK DETECT. The SPUR_CRL bit is set to 1 only in the GPS mode with the LMX2532LQ1065 when a 19.68 MHz reference oscillator is used. The RF N counter consists of the 4-bit programmable counter (RF_B counter), the 3-bit swallow counter (RF_A counter) and the 11-bit delta sigma modulator (RF_FN counter) ...
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... Prescaler Values: Device Type LMX2522 LMX2532 RF_B: Preset divide ratio of binary 4-bit programmable counter (2 ≤ RF_B ≤ 15) RF_A: Preset divide ratio of binary 3-bit swallow counter (0 ≤ RF_A ≤ 7 for prescaler ≤ RF_A ≤ 5 for prescaler of 6) RF_FN: Preset numerator of binary 11-bit modulus counter (0 ≤ RF_FN = 19 ...
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... The R1 register address bits (R1 [1:0]) are “01”. The IF_FREQ bits selects the default IF frequency applicable to the specific CDMA system. For the LMX2522 the default IF frequency is 440.76 MHz, and for the LMX2532 the default IF frequencies are 367.20 MHz and 170.76 MHz, depending on variant. ...
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Programming Description R2 REGISTER The R2 Register address bits (R2 [1:0]) are “10”. The IF_CUR [1:0] bits program the IF charge pump current. Considering the external IF VCO and loop filter, the user can select the amount of IF charge ...
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Programming Description R3 REGISTER The R3 register address bits (R3 [2:0]) are “011”. Register R3 contains the controls for the phase lock bandwidth controls (BW_DUR, BW_CRL and BW_EN). The duration of the digital controller portion of the bandwidth control is ...
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Programming Description R4 REGISTER The R4 register address bits (R3 [3:0]) are “0111”. Register R4 is used to set the IF N counters if the default value is not desired. This register is only active if the SPI_DEF bit in ...
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Programming Description R6 REGISTER The R6 register address bits (R6 [5:0]) are “011111”. Register R6 is used for internal testing of the device and is not intended for customer use. This register is only active if the SPI_DEF bit in ...
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... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...