mc100ep195 ON Semiconductor, mc100ep195 Datasheet - Page 4

• Manufacturer Part Number: mc100ep195
• Description: 3.3v Ecl Programmable Delay Chip
• Manufacturer: ON Semiconductor

Table 2. CONTROL PIN
3. Internal pulldown resistor will provide a logic LOW if pin is left unconnected.
Table 3. CONTROL D[0:10] INTERFACE
4. Short V
5. When Operating in LVTTL Mode, the reference voltage can be provided by connecting an external resistor, R
is 2.2 kW $5%), between V
SETMAX
SETMIN
LEN
D10
V
V
V
Pin
EN
CF
CF
CF
CF
(pin 8) and V
Table 4. DATA INPUT ALLOWED OPERATING VOLTAGE MODE TABLE
Table 5. ATTRIBUTES
6. For additional information, see Application Note AND8003/D.
Internal Input Pulldown Resistor
ESD Protection
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 6)
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
PECL Mode Operating Range
NECL Mode Operating Range
EF
V
1.5 V $ 100 mV
(pin 7).
LOW (Note 3)
LOW (Note 3)
LOW (Note 3)
LOW (Note 3)
LOW (Note 3)
EF
CF
POWER SUPPLY
No Connect
Pin (Note 4)
and V
HIGH
HIGH
HIGH
HIGH
HIGH
State
EE
pins.
Characteristics
Input Signal is Propagated to the Output
Output Holds Logic Low State
Transparent or LOAD mode for real time delay values present on D[0:10].
LOCK and HOLD mode for delay values on D[0:10]; further changes on D[0:10]
are not recognized and do not affect delay.
Output Delay set by D[0:10]
Set Minimum Output Delay
Output Delay set by D[0:10]
Set Maximum Output Delay
CASCADE Output LOW, CASCADE Output HIGH
CASCADE Output LOW, CASCADE Output HIGH
ECL Mode
LVCMOS Mode
LVTTL Mode (Note 5)
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Charged Device Model
Human Body Model
CONTROL DATA SELECT INPUTS PINS (D [0:10])
LVCMOS
YES
N/A
Machine Model
4
LQFP−32
QFN−32
(R1)
LVTTL
YES
N/A
Pb Pkg
Level 2
UL 94 V−0 @ 0.125 in
LVPECL
Function
−
YES
N/A
1217 Devices
> 100 V
> 2 kV
> 2 kV
Value
75 kW
Pb−Free Pkg
LVNECL
Level 2
Level 1
YES
N/A
CF
(suggested resistor value