mc100es6030 Integrated Device Technology, mc100es6030 Datasheet

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mc100es6030

Manufacturer Part Number
mc100es6030
Description
Lvcmos-input Lvpecl Output Triple Flip-flop 1.2-ghz
Manufacturer
Integrated Device Technology
Datasheet
IDT™ 2.5/3.3V ECL Triple D Flip-Flop with Set and Reset
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
2.5/3.3V ECL Triple D Flip-Flop with
Set and Reset
SEMICONDUCTOR TECHNICAL DATA
Preliminary Information
2.5/3.3V ECL Triple D Flip- - Flop
with Set and Reset
outputs. When the clock input is low, data enters the master latch and
transfers to the slave during a positive transition on the clock input.
The Set and Reset inputs are asynchronous and override the clock
inputs.
Features
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
©
1.2 GHz minimum toggle frequency
450 ps typical propagation delay
LVPECL operating range: V
LVECL operating range: V
20--lead SOIC package
Ambient temperature range --40°C to +85°C
The MC100ES6030 is a triple master--slave D flip--flop with differential
Each flip--flop has individual Reset inputs while the Set input is shared.
V
S012
Figure 1. 20- -Lead Pinout (Top View) and Logic Diagram
Motorola, Inc. 2003
CC
20
1
S
Q0
19
D0
Q
2
CLK0
Q0
18
3
Q
R
V
R0
17
4
CC
S
Q1
16
D1
Q
5
CC
CC
= 0 V, V
= 2.375 V to 3.8 V, V
CLK1
Q1
15
6
Q
Freescale Semiconductor, Inc.
R
For More Information On This Product,
EE
V
14
R1
CC
7
1
= --2.375 V to --3.8 V
S
Q2
D2
13
Q
8
Go to: www.freescale.com
CLK2
Q2
12
9
Q
EE
R
= 0 V
V
R2
11
10
EE
1
Z = LOW to HIGH Transition
X = Don’t Care
R0- -R2
S012
Q0- -Q2, Q0- -Q2
V
MC100ES6030DW
MC100ES6030DWR2
D0- -D2
CLK0- -CLK2
V
EE
CC
R
L
L
H
L
H
PIN
MC100ES6030
Device
ORDERING INFORMATION
S
L
L
L
H
H
20- -LEAD SOIC PACKAGE
PIN DESCRIPTION
TRUTH TABLE
DW SUFFIX
CASE 751D
D
L
H
X
X
X
Order Number: MC100ES6030
ECL Data Inputs
ECL Reset Inputs
ECL Clock Inputs
ECL Common Set Input
ECL Differential Data Outputs
Positive Supply
Negative Supply
CLK
Z
Z
X
X
X
MC100ES6030
FUNCTION
DATA SHEET
Package
Undef
SO- -20
SO- -20
Rev 0, 10/2003
Q
L
H
L
H
Undef
MC100ES6030
Q
H
L
H
L

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mc100es6030 Summary of contents

Page 1

... ECL Triple D Flip-Flop with with Set and Reset Set and Reset The MC100ES6030 is a triple master--slave D flip--flop with differential outputs. When the clock input is low, data enters the master latch and transfers to the slave during a positive transition on the clock input. ...

Page 2

... V - -1025 V - -955 V - -880 -1555 V - -1810 V - -1705 V - -1620 -880 V - -1165 V - -880 -1475 V - -1810 V - -1475 CC CC ±150 ±150 = 0 V for V = 2.5 V operation is supported, but TT CC TIMING SOLUTIONS NETCOM Units °C °C EE Unit µV MC100ES6030 ...

Page 3

... V ±5% or 3.135 25°C 85°C Typ Max Min Typ Max 1.2 600 0 150 0 100 200 100 100 200 100 400 650 < 2 < 2 TBD TBD TBD TBD TBD D Receiver Device MOTOROLA NETCOM = Unit GHz MC100ES6030 ...

Page 4

... SHALL NOT EXCEED 0.25mm PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.62mm. ° ° TIMING SOLUTIONS NETCOM MC100ES6030 ...

Page 5

... MPC92459 MC100ES6030 PART NUMBERS 900 MHz Low Voltage LVDS Clock Synthesizer 2.5/3.3V ECL Triple D Flip-Flop with Set and Reset INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc ...

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