mc88lv926 Integrated Device Technology, mc88lv926 Datasheet
mc88lv926
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mc88lv926 Summary of contents
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... V supply. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it to multiple locations on a board. The PLL also allows the MC88LV926 to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. Features • ...
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... QCLKEN GND RST_OUT(LOCK) PLL_EN Figure 7) the lock time is approximately 10ms. reaches the CC Unit Test Conditions 25° 3 25°C Advanced Clock Drivers Device Data Freescale Semiconductor NETCOM ramp CC MC88LV926 ...
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... I Minimum Dynamic Output Current OLD I OHD Maximum Quiescent Supply Current The MC88LV926 can also be operated from a 3.3V supply. V unchanged, except V ; when +12mA for the RST_OUT output Maximum test duration 2.0ms, one output loaded at a time. 4. The PLL_EN input pin is not guaranteed to meet this specification. ...
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... Maximum SYNC Input Period is 125 ns. CC MC88LV926 IDT™ Low Skew CMOS PLL 68060 Clock Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 4 CH VCO PUMP 0 1 Figure 2. MC88LV926 Logic Block Diagram Parameter (1) 4 RST_OUT Q 2X_Q ÷ ÷ ...
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... Into a 50 Ω Load Terminated (See Timing Diagram in – CC Figure Into a 50 Ω Load 13.5 ns Terminated – ns – ns When in Phase–Lock – ns See Application Notes, 16.5 ns See Application Notes, 1024 ‘Q' Cycles ns (512 Q/2 Cycles) MC88LV926 NETCOM Unit MHz MHz / Note 5 Note 5 MC88LV926 5 ...
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... IDT™ Low Skew CMOS PLL 68060 Clock Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 6 APPLICATION NOTES ensure no jitter is present on the MC88LV926 outputs. This technique causes a phase offset between the SYNC input and the Q0 output, measured at the pins. The t PD process, temperature, and voltage ...
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... QCLKEN t SKEWQCLKEN NOTES: 1. The MC88LV926 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50% duty cycle. 2. All skew specs are measured between the V as “windows”, not as a ± deviation around a center point. ...
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... NOTE: Further loop optimization may occur. 10 μF Low Freq Bias Figure 7. Recommended Loop Filter and Analog Isolation Scheme for the MC88LV926 MC88LV926 IDT™ Low Skew CMOS PLL 68060 Clock Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc ...
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... Low Skew CMOS PLL 68060 Clock Driver 16.67 MHz X–TAL Oscillator System Reset Figure 8. Typical MC88LV926/MC68060 System Configuration IDT™ Low Skew CMOS PLL 68060 Clock Driver Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor ...
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... PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 7˚ 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR 0˚ PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE WIDTH TO EXCEED 0.62 MM. Advanced Clock Drivers Devices Freescale Semiconductor NETCOM MC88LV926 ...
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... MPC92459 MC88LV926 PART NUMBERS 900 MHz Low Voltage LVDS Clock Synthesizer Low Skew CMOS PLL 68060 Clock Driver INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc ...