nb6l295m ON Semiconductor, nb6l295m Datasheet
nb6l295m
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nb6l295m Summary of contents
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... The SDI input pins are controlled by LVCMOS or LVTTL level signals. The NB6L295M 16 mA CML output contains temperature compensation circuitry. This device is offered 24-pin QFN Pb-free package. The NB6L295M is a member of the ECLinPS MAX™ family of high performance products. • ...
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... NB6L295M Figure 1. Simplified Functional Block Diagram http://onsemi.com 2 ...
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... VCC1s are connected to each other: VCC0 and VCC1 are separate. NB6L295M VT0 IN0 IN0 VT0 GND VCC0 NB6L295M VT1 IN1 IN1 VT1 GND VCC1 Figure 2. Pinout: QFN-24 (Top View) ...
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... Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. NB6L295M Characteristics Human Body Model Machine Model ...
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... IH IL, ISE single-ended mode and V parameters must be complied with simultaneously. IHD ILD, ID CMR 9. V (min) varies 1:1 with voltage on GND pin, V CMR the differential input signal. NB6L295M CC0 CC1 and Outputs Open) (Sum 3 CC0 ...
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... Extended Mode INx to Qx/INx to Qx D[8: D[8: Step Delay (Selected D Bit HIGH All Others LOW) D0 HIGH D1 HIGH D2 HIGH D3 HIGH D4 HIGH D5 HIGH D6 HIGH D7 HIGH D8 HIGH NB6L295M = 2.375 V to 3.6 V, GND = CC0 CC1 Characteristic ≤ 1.5 GHz ) f INPPmin in IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1 IN0/IN0 to Q1/Q1 D[8: D[8: ...
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... Serial Data Interface Programming The NB6L295M is programmed by loading the 11-Bit SHIFT REGISTER using the SCLK, SDATA and SLOAD inputs. The 11 SDATA bits are 1 PSEL bit, 1 MSEL bit and 9 delay value data bitsD[8:0]. A separate 11-bit load cycle is required to program the delay data value of each channel, PD0 and PD1. For example, at powerup two load cycles will be needed to initially set PD0 and PD1 ...
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... LOW (enabled) for functional delay operation. EN LSB PSEL MSEL D0 SDIN SCLK C0 C1 SLOAD t SDIN to s SCLK t SDIN to SCLK h Figure 8. SDI Programming Cycle Timing Diagram (Load Cycle NB6L295M Q0/Q0 MSEL 0 1 11-Bit Shift Register Load Cycle Required for Each Channel http://onsemi.com 8 ...
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... NB6L295M (Decimal) MSEL (0) 0 (1) 0 (2) 0 (3) 0 (4) 0 (5) 0 (6) 0 (7) 0 (8) 0 • • • (16) ...
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... Driven Differentially IHD(MAX) V ILD(MAX) V IHD CMR ID V ILD V IHD(MIN) V ILD(MIN) GND Figure 15. V Diagram CMR NB6L295M Figure 10. Typical CML Output Structure thmax thmin GND INx INx Figure 14. Differential Inputs Driven INx INx IHD ILD Figure 16 ...
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... GND GND Single-Ended Driver GND GND Figure 21. Capacitor-Coupled Single-Ended ; Interface (V Bypassed to Ground with 0.1 mF Capacitor) V REFAC http://onsemi.com INx NB6L295M = INx GND Figure 18. LVDS Interface CC V ...
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... Figure 23. Output Voltage Amplitude (V Output Frequency at Ambient Temperature (Typical) ORDERING INFORMATION Device NB6L295MMNG NB6L295MMNTXG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NB6L295M ...
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... FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A2 0.60 0.80 A3 0.20 REF b 0.23 0.28 D 4.00 BSC D2 2.70 2.90 E 4.00 BSC E2 2.70 2.90 e 0.50 BSC L 0.35 0.45 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NB6L295M/D ...