w83194br-b Winbond Electronics Corp America, w83194br-b Datasheet
w83194br-b
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w83194br-b Summary of contents
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... W83194BR-B W83194BG-B Winbond Clock Generator For INTEL P4 845 Series Chipset Date: 10/02/2006 Revision: 3.1 ...
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... CLOCK GEN. FOR INTEL P4 845 SERIES CHIPSET W83194BR-B Datasheet Revision History PAGES DATES VERSION 1 n.a. 2 n.a. 4/1/02 1 10/1/02 1.1 4 All 2/25/03 2.0 5 3/18/03 3.0 6 10/02/06 3 W83194BR-B/W83194BG-B WEB MAIN CONTENTS VERSION All of the versions before 0.50 are for internal n.a. use. 1.0 Change version and version on web site to 1.0 Modify ratio table of CPU, 3V66, and PCI clock 1 ...
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... Register 12: Winbond Chip ID Register (Read Only) ....................................................................14 7.14 Register 13: SEL24_48 and FIX_3V66_PCI Control.....................................................................14 7.15 Register 14: Control the period of spread spectrum ......................................................................15 7.16 Register 15: Slew Rate Control ......................................................................................................15 7.17 Register 16: Slew Rate Control ......................................................................................................16 7.18 Register 17: Slew Rate Control ......................................................................................................16 7.19 Register 81: Winbond Test Register I.............................................................................................16 7.20 Register 82: Winbond Test Register II............................................................................................16 8. ACCESS INTERFACE ................................................................................................................. 17 8.1 Block Write protocol ........................................................................................................................17 W83194BR-B/W83194BG ...
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... Register 13: SEL24_48 and FIX_3V66_PCI Control.....................................................................26 1.3 Register 14: Control the period of spread spectrum ......................................................................27 1.4 Register 15: Slew Rate Control ......................................................................................................28 1.5 Register 16: Slew Rate Control ......................................................................................................28 1.6 Register 17: Slew Rate Control ......................................................................................................29 2. TOP MARKING DIFFERENCE BETWEEN VERSION A AND VERSION B. .............................. 30 W83194BR-B/W83194BG-B Publication Release Date: October 2006 - III - Revision 3.1 ...
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... The W83194BR-B also has watch dog timer and reset output pin to support auto-reset when systems hanging caused by improper frequency setting. The W83194BR-B accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± ...
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... CLOCK GEN. FOR INTEL P4 845 SERIES CHIPSET 3. PIN CONFIGURATION ^: These outputs have 1 drive strength &: Internal Pull-down resistor 120K to GND W83194BR-B/W83194BG-B #: Active low *: Internal pull up resistor 120K to VDD - 2 - ...
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... tro & W83194BR-B/W83194BG ...
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... Internal 120kΩ pull-up & Internal 120kΩ pull-down ^ 1.5X~2X strength 5.1 Crystal I/O PIN PIN NAME 3 XIN 4 XOUT W83194BR-B/W83194BG-B DESCRIPTION TYPE Crystal input with internal loading capacitors (18pF) and IN feedback resistors. Crystal output at 14.318MHz nominally with internal loading OUT capacitors (18pF DESCRIPTION ...
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... VCH_CLK 31 & FS4 PCICLK8^ 5 & FS0 W83194BR-B/W83194BG-B TYPE Differential clock outputs for host frequencies of CPU and OUT chipset Power on trapping for different current reference. The reference current is referred for Pin 37 (IREF). This pin is IN latched during VTT_PWRGD. This pin is internal pull up 120K ...
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... FS2 34 48MHz_DOT 48MHz_USB 35 & FS3 W83194BR-B/W83194BG-B TYPE OUT PCI clock output. This pin is with x1 driving strength. Latched input for FS1 at initial power up for H/W selecting the IN output frequency of CPU, 3V66 and PCI clocks. This is td120k internal 120K pull down. OUT PCI clock outputs. This pin is with x1 driving strength. ...
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... VDDA 33 AVDD48 4, 8, 14, 19, 25, 29, 32, GND 36, 42 W83194BR-B/W83194BG-B TYPE PWR 3.3V power supply for REF. PWR 3.3V power supply for PCI. PWR 3.3V power supply for 3V66. PWR 3.3V power supply for CPU. PWR 3.3V power supply for analog core. PWR Analog power 3.3V for 48MHz PWR Ground pin for 3 ...
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... W83194BR-B/W83194BG-B FS0 CPU (MHZ) 3V66(MHZ) 0 100.8 67.2 1 100.0 66.6 0 101.1 67.4 1 104.9 69.9 0 107.1 71.4 1 109.0 72.7 0 100.0 66.6 1 114.0 76.0 0 117.0 78.0 1 120.1 80.0 0 126.9 84.6 1 130.0 86.6 0 133.3 88.8 1 170 ...
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... W83194BR-B/W83194BG-B Enable Spread Spectrum in the frequency table Normal 1 = Spread Spectrum enabled Frequency selection by software via Enable software program FS [4:0 Select frequency by hardware. 1= Select frequency by software I Enable reload safe frequency when the watchdog is timeout. ...
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... Register 4: 3V66 Control Register (1 = Enable Stopped) BIT PIN NO. PWD W83194BR-B/W83194BG-B X MULTISEL0 trapping pin data read back 1 PCICLK 6 1 PCICLK 5 1 PCICLK 4 1 PCICLK 3 1 PCICLK 2 1 PCICLK 1 1 PCICLK 0 1 48MHZ_DOT 1 48MHZ_USB 1 REF ...
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... WD_TIME [3] 2 WD_TIME [2] 1 WD_TIME [1] 0 WD_TIME [0] W83194BR-B/W83194BG-B 0 Reserved Enable Watchdog Timer if set to 1. Set to 0, disable watchdog timer. This bit is trapping pin during VTT_PWRGD#. Read this X bit will return a counting state. If timers continue down count, this bit will return 1. Otherwise, this bit will return 0. ...
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... SP_UP [0] 3 SP_DOWN [3] 2 SP_DOWN [2] 1 SP_DOWN [1] 0 SP_DOWN [0] W83194BR-B/W83194BG-B Programmable N divisor value. Bit 7 ~0 are defined in the X Register 8. X Test bit 1. Winbond test bit, do not change them. X Test bit 0. Winbond test bit, do not change them Programmable M divisor value. ...
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... RATIO PWD 0 Winbond Chip ID. W83194BR-B is 0x32. 0 Winbond Chip ID. 1 Winbond Chip ID. 1 Winbond Chip ID. 0 Winbond Chip ID. 0 Winbond Chip ID. 1 Winbond Chip ID. 0 Winbond Chip ID DESCRIPTION VCO / 3V66 VCO / PCI RATIO ...
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... SEL24_48 6 Iref_test0 5 FIX_3V66_PCI 4 SEL [1] 3 SEL [0] 2 CPU_PCI_SKEW [2] 1 CPU_PCI_SKEW [1] 0 CPU_PCI_SKEW [0] W83194BR-B/W83194BG-B PWD 1 Winbond Master-Chip ID. 0 Winbond Master-Chip ID. 0 Winbond Sub-Chip ID. 1 Winbond Sub-Chip ID. 0 Winbond Master’s Version ID. 1 Winbond Master’s Version ID. 0 Winbond Sub’s Version ID. ...
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... S1:S2 10/ 7.16 Register 15: Slew Rate Control BIT NAME 7 REF_S1 6 REF_S1_N 5 REF_S2 4 REF_S2_N 3 3V66_S1 2 3V66_S1_N 1 3V66_S2 0 3V66_S2_N W83194BR-B/W83194BG-B PWD 0 Reserved 0 Reserved Program the period of spread spectrum S1_N: S2_N 01/10 Normal 00 Strong 11 Weak PWD 0 1 Pin 48 REF output slew rate control bit. ...
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... U48M_S2 0 U48M_S2_N 7.19 Register 81: Winbond Test Register I BIT NAME 7:0 TEST_REG1 7.20 Register 82: Winbond Test Register II BIT NAME 7:0 TEST_REG2 W83194BR-B/W83194BG-B PWD 1 0 Pin 5,6,9, PCICLK [0,7,8] output slew rate control bit This slew rate status default is Strong Pin 10,11,12,15,16,17 PCICLK [1:6] output slew rate control 0 bit 0 This slew rate status default is Normal ...
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... CLOCK GEN. FOR INTEL P4 845 SERIES CHIPSET 8. ACCESS INTERFACE 2 The W83194BR-B provides I C Serial Bus for microprocessor to read/write internal registers. In the W83194BR-B is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I address is defined at 0xD2. 8.1 Block Write protocol 8.2 Block Read protocol ## In block mode, the command code must filled 00H 8 ...
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... Input ESD protection (Human body model) 9.2 General Operating Characteristics VDDREF =VDDA=VDDCPU=VDD3V66=VDDPCI=AVDD48= 3.3V Cl=10pF PARAMETER SYMBOL Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Dynamic Supply Current Input pin capacitance Output pin capacitance Input pin inductance W83194BR-B/W83194BG-B MIN MAX UNITS 0.4 V ...
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... Cycle to Cycle jitter Duty Cycle 9.5 CPU 1.0V Electrical Characteristics ± VDDA=VDDC= 3. Voh=0.8V, Vr=221, IREF=5.0mA, Ioh=4*IREF PARAMETER Rise Time Fall Time Absolute crossing point Voltages Cycle to Cycle jitter Duty Cycle W83194BR-B/W83194BG-B MIN TYP MAX UNITS 1 2 150 ps 175 ps 500 ...
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... VDDPCI= 3. PARAMETER Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max W83194BR-B/W83194BG-B ° ° +70 C, Test load, Cl=10pF, MIN MAX UNITS 500 1600 ps 500 1600 ...
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... VDD48= 3. +70 PARAMETER Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max W83194BR-B/W83194BG-B ° C, Test load, Cl=10pF, MIN MAX UNITS 1000 4000 ps 1000 4000 ps 500 ...
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... W83194BG-B 11. HOW TO READ THE TOP MARKING W83194BR-B 28051234 320GBASB 1st line: Winbond logo and the type number: Normal:W83194BR-B, Lead free: W83194BG-B 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 942 320: packages made in '2003, week 20 G: assembly house ID ...
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... CLOCK GEN. FOR INTEL P4 845 SERIES CHIPSET 12. PACKAGE DRAWING AND DIMENSIONS W83194BR-B/W83194BG-B Publication Release Date: October 2006 - 23 - Revision 3.1 ...
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... CLOCK GEN. FOR INTEL P4 845 SERIES CHIPSET VERSION CHANGE NOTICE 1 1. DESCRIPTION: 1. This version change notice is for W83194BR changed from A version to B version only for customers who use A version. If you have never used A version, you can skip the following contents. ...
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... VERSION B BIT NAME 7 MAS_ID[1] 6 MAS_ID[0] 5 SUB_ID[1] 4 SUB_ID[0] 3 MAS_VER_ID[1] 2 MAS_VER_ID[1] 1 SUB_VER_ID[1] 0 SUB_VER_ID[1] Note: Register 12 Default value in Version A is 11H Version B is 95H. W83194BR-B/W83194BG-B Ratio Table VERSION B VCO/CPU VCO/ 3V66 VCO/PCI VCO/CPU VCO/ 3V66 VCO/PCI ...
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... FIX_3V66_PCI 4 SEL [1] 3 SEL [0] 2 CPU_PCI_SKEW [2] 1 CPU_PCI_SKEW [1] 0 CPU_PCI_SKEW [0] W83194BR-B/W83194BG-B PWD Pin 34, 48MHz_DOT output frequency select bit 0 SEL24_48=0, 48MHz_DOT=48MHz(Default) SEL24_48=1, 48MHz_DOT=24MHz 0 Control CPU_I/O Buffer Bias Current 0 0: normal mode, 1: fix mode 0 3V66 & PCI FIX frequency (PCI=3V66/2) SEL [1:0] for 3V66, PCI, When bit 5 set 1 these bit had ...
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... SPCNT [1] 0 SPCNT [0] Note: The Register 15:17 slew rate control select bit fit value Please fellow below table. The S1_N is S1 complementary and S2_N is S2 complementary, please fit complementary value. S1:S2 10/ W83194BR-B/W83194BG-B PWD 0 Reserved 0 Reserved Program the period of spread spectrum. ...
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... PCIF_S1 6 PCIF_S1_N 5 PCIF_S2 4 PCIF_S2_N 3 PCI_S1 2 PCI_S1_N 1 PCI_S2 0 PCI_S2_N W83194BR-B/W83194BG-B PWD 0 Pin 48 REF output slew rate control bit. 1 This slew rate status default is Weak Pin 20,21,22, 3V66 [1:3] output slew rate control bit. This slew rate status default is Normal PWD ...
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... U48M_S1 2 U48M_S1_N 1 U48M_S2 0 U48M_S2_N W83194BR-B/W83194BG-B PWD 1 0 Pin 31 3V66_0/VCH output slew rate control bit. This slew rate status default is Normal Pin 34,35 48MHz_USB, 48MHz_DOT output slew rate control 0 bit. 0 This slew rate status default is Normal ...
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... CLOCK GEN. FOR INTEL P4 845 SERIES CHIPSET 2. TOP MARKING DIFFERENCE BETWEEN VERSION A AND VERSION B. Version B W83194BR-B 28051234 814GAASB SB included W83194BR-B Version Change Notices List DATE VERSION 1 10/02/ W83194BR-B/W83194BG-B Version A W83194BR-B 28051234 814GAA Without SB REMARK Release Notice for A version to B version. ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83194BR-B/W83194BG-B Important Notice Publication Release Date: October 2006 - 31 - ...