idt49fct805ctsob Integrated Device Technology, idt49fct805ctsob Datasheet - Page 6

• Manufacturer Part Number: idt49fct805ctsob
• Description: Fast Cmos Buffer/clock Driver
• Manufacturer: Integrated Device Technology

IDT49FCT805BT/CT, 806BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUIT FOR ALL OUTPUTS
PACKAGE DELAY
PULSE SKEW - t
ENABLE AND DISABLE TIMES
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
2. Pulse Generator for All Pulses: f
OUTPUT
Generator
Disable-HIGH
INPUT
Pulse
OUTPUT
NORMALLY
NORMALLY
CONTROL
INPUT
OUTPUT
OUTPUT
INPUT
HIGH
LOW
V
IN
SWITCH
CLOSED
SWITCH
OPEN
ENABLE
R
t
t
SK
t
PZL
PZH
t
PLH
T
PLH
t
D.U.T.
(p)
SK(p)
t
V
R
CC
= |t
1.5V
1.5V
3.5V
0V
1.0MHz; t
PHL -
V
OUT
t
t
PLH
PHZ
DISABLE
t
t
PHL
PHL
F
|
C
50pF
t
t
2.5ns; t
PLZ
L
F
0.3V
0.3V
R
500
500
0.8V
2.0V
V
3V
1.5V
0V
1.5V
V
2.5ns
OH
OL
3V
1.5V
0V
3.5V
V
0V
V
2920 drw 08
2920 drw 10
2920 drw 12
3V
1.5V
0V
1.5V
V
V
OH
OL
2920 drw 07
OL
OH
7.0V
9.2
PACKAGE 1 OUTPUT
PACKAGE 2 OUTPUT
OUTPUT SKEW- t
PACKAGE SKEW - t
Package 1 and Package 2 are same device type and speed grade
ENABLE AND DISABLE TIME
SWITCH POSITION
DEFINITIONS:
C
R
L
T
= Load capacitance: includes jig and probe capacitance.
= Termination resistance: should be equal to Z
OUTPUT 1
OUTPUT 2
Generator.
INPUT
Disable HIGH
Disable LOW
Enable HIGH
Enable LOW
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INPUT
Test
t
SK(o)
SK
t
PLH1
t
= |t
SK(t)
(o)
t
SK
PLH2
t
PLH1
t
PLH2 -
SK(o)
t
(t)
= |t
PLH2
t
SK(t)
PLH2 -
t
PLH1
t
t
|
PHL1
PLH1
t
or
t
PHL2
PHL1
t
SK(o)
|t
t
PHL2 -
PHL2
OUT
|
or
Switch
Closed
t
Open
SK(t)
|t
of the Pulse
PHL2 -
t
PHL1
V
V
3V
1.5V
0V
V
1.5V
V
1.5V
t
|
PHL1
OL
OL
OH
OH
2920 drw 09
2920 drw 11
V
V
V
3V
1.5V
0V
1.5V
1.5V
V
2920 lnk 08
OH
OL
OH
OL
|
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