lmk03200 National Semiconductor Corporation, lmk03200 Datasheet
lmk03200
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lmk03200 Summary of contents
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... Precision 0-Delay Clock Conditioner with Integrated VCO General Description The LMK03200 family of precision clock conditioners com- bine the functions of jitter cleaning/reconditioning, multiplica- tion, and 0-delay distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high per- formance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations ...
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Functional Block Diagram www.national.com 2 30088701 ...
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Connection Diagram 48-Pin LLP Package 3 30088702 www.national.com ...
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Pin Descriptions Pin # 13, 16, 19, 22, Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, Vcc8, Vcc9, Vcc10, 26, 30, 31, 33, 37, 40, 43 14, ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Parameter Power Supply Voltage Input Voltage Storage Temperature Range Lead Temperature (solder 4 s) Junction Temperature Recommended Operating Conditions ...
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Electrical Characteristics ≤ ≤ ≤ (3.15 V Vcc 3.45 V, -40 ° most likely parametric norms at Vcc = 3 characterization and are not guaranteed). Symbol Parameter Power Supply Current I CC (Note ...
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... PLL_CP_GAIN = 32x VCO LMK03200 After programming R15 for lock, only changes 0_DELAY_MODE and PLL_N for the purpose of enabling 0- delay mode permitted to guarantee continuous lock. (Note 9) LMK03200 °C A LMK03200 LMK03200 Clock Skew and Delay Equal loading and identical clock configuration = 100 Ω ...
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Symbol Parameter Clock Distribution Section - LVDS Clock Outputs (Note 12) Jitter Additive RMS Jitter (Note 12) ADD V Differential Output Voltage OD Change in magnitude of V ΔV OD complementary output states V Output Offset Voltage OS Change in ...
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Symbol Parameter t Data to Clock Set Up Time CS t Data to Clock Hold Time CH t Clock Pulse Width High CWH t Clock Pulse Width Low CWL t Clock to Enable Set Up Time ES t Enable to ...
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Charge Pump Current Specification Definitions I1 = Charge Pump Sink Current Charge Pump Sink Current Charge Pump Sink Current Charge Pump Source Current Charge ...
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Typical Performance Characteristics LVDS Vod LVDS Output Buffer Noise Floor (Note 17) Delay Noise Floor (Notes 17, 18) Note 16: These plots show performance at frequencies beyond what the part is guaranteed to operate at to give the user an ...
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... AC grounding OSCin* with a 0.1 µF capac- itor. 1.4 LOW NOISE, FULLY INTEGRATED VCO The LMK03200 family of devices contain a fully integrated VCO. For proper operation the VCO uses a frequency cali- bration routine. The frequency calibration routine is activated any time that the R15 register is programmed and 0_DELAY_MODE = 0 ...
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GLOBAL CLOCK OUTPUT SYNCHRONIZATION The SYNC* pin synchronizes the clock outputs. When the SYNC* pin is held in a logic low state, the divided outputs are also held in a logic low state. The bypassed outputs will con- tinue ...
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DIGITAL LOCK DETECT The PLL digital lock detect circuitry compares the difference between the phase of the inputs of the phase detector generated delay of ε. To indicate a locked state the phase error must be ...
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... Note possible to use the indi- vidual delays on each clock output (CLKoutX_DLY) to further 1.13 0-DELAY MODE The LMK03200 family can feedback an output to the phase detector either internally using CLKout5 or CLKout6, or ex- ternally by routing any clock output back to the FBCLKin/ FBCLKin* input port to be synchronized with the reference clock for 0-delay output ...
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... General Programming Information The LMK03200 family of devices are programmed using sev- eral 32-bit registers which control the device's operation. The registers consist of a data field and an address field. The last 4 register bits, ADDR [3:0] form the address field. The re- maining 28 bits form the data field DATA [27:0]. ...
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PLL_MUX value to indicate the device is phase locked. 0_DELAY_MODE = 1 reverts the LD pin back to digital lock detect. The device is now phase locked and synchronized with the reference clock. ...
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Begin monitoring LD pin for frequency calibration routine complete signal. The device now begins the frequency calibration routine, when it completes the LD pin will go high since PLL_MUX was programmed with the active high option for the frequency ...
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CLKout0_EN CLKout1_EN CLKout2_EN CLKout3_EN CLKout4_EN CLKout5_EN CLKout6_EN CLKout7_EN 0_DELAY_ MODE DLD_MODE2 RESET Register 19 www.national.com ...
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DIV4 Vboost Register www.national.com POWERDOWN EN_CLKout_Global EN_Fout 20 ...
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Register Registers R0 through R7 control the eight clock outputs. Reg- ister R0 controls CLKout0, Register R1 controls CLKout1, and so on. There are some additional bit in register R0 called RE- SET, DLD_MODE2, 0_DELAY_MODE, and ...
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FB_MUX [1:0] -- Feedback Mux This bit is only in register R0 and is for use with the 0-delay mode. FB_MUX [1:0] 0 CLKout5 (default) 1 FBCLKin/FBCLKin* Input 2 3 When using CLKout5 and FBCLKin/FBCLKin* for feedback for 0-delay ...
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CLKoutX_DLY [3:0] -- Clock Output Delays These bits control the delay stages for each clock output. In order for these delays to be active, the respective CLKoutX_MUX bit must be set to either "Delayed" or "Divided and Delayed" mode. ...
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VCO_R4_LF [2:0] -- Value for Internal Loop Filter Resistor R4 These bits control the R4 resistor value in the internal loop filter. The recommended setting for VCO_R4_LF[2: for optimum phase noise and jitter. VCO_R4_LF[2:0] Low (~200 Ω) ...
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POWERDOWN bit -- Device Power Down This bit can power down the device. Enabling this bit powers down the entire device and all blocks, regardless of the state of any of the other bits or pins. POWERDOWN bit 0 ...
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PLL_CP_GAIN [1:0] -- PLL Charge Pump Gain These bits set the charge pump gain of the PLL. PLL_CP_GAIN [1:0] Charge Pump Gain www.national.com 2.10.4 PLL_N_DLY [3:0] - Global Skew Adjust, Lead These bits control the ...
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... Application Information 3.1 SYSTEM LEVEL DIAGRAM Figure 6 shows an LMK03200 family device used in a typical application. In this setup the clock may be multiplied, recon- ditioned, and redistributed. Both the OSCin/OSCin* and CLK- outX/CLKoutX* pins can be used in a single-ended or a differential fashion, which is discussed later in this datasheet. ...
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... Clock Conditioner Owner's Manual provided by National Semicon- ductor. When designing with the integrated loop filter of the LMK03200 family, considerations for minimum resistor ther- mal noise often lead one to the decision to design for the minimum value for integrated resistors, R3 and R4. Both the www ...
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CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS Due to the myriad of possible configurations the following ta- ble serves to provide enough information to allow the user to Table 3.5 - Block Current Consumption Block Condition Entire device, All outputs ...
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... DC voltage (common mode voltage). For example, when driving the OSCin/OSCin* input of the LMK03200 fam- ily, OSCin/OSCin* should be AC coupled because OSCin/ OSCin* biases the signal to the proper DC level, see Figure 6 ...
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FIGURE 9. Differential LVPECL Operation, DC Coupling FIGURE 10. Differential LVPECL Operation, DC Coupling, Thevenin Equivalent 3.7.2 Termination for AC Coupled Differential Operation AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver standards. ...
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... It is possible to use an LVPECL driver as one or two separate 800 mV p-p signals. When DC coupling one of the LMK03200 family clock LVPECL drivers, the termination should still be 50 ohms to Vcc - shown in Figure 13. Again the Thevenin equivalent circuit (120 Ω resistor connected to Vcc and an 82 Ω ...
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... At the recommended power level the 30088724 PLL phase noise degradation from full power operation (8 dBm) is less than 2 dB. an LMK03200 device with eight LMK01000 family devices clocks may be distributed in many different LVDS / LVPECL combinations. It's possible to distribute more than 64 clocks by adding more LMK01000 family devices. Refer to AN-1864 for more details ...
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... TERMINOLOGY The differential voltage of a differential signal can be de- scribed by two different definitions causing confusion when reading datasheets or communicating with other engineers. This section will address the measurement and description of a differential signal so that the reader will be able to under- stand and discern between the two different definitions when used ...
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... Physical Dimensions inches (millimeters) unless otherwise noted Ordering Information Order Number VCO Version LMK03200ISQX 1.24 GHz LMK03200ISQ 1.24 GHz LMK03200ISQE 1.24 GHz Leadless Leadframe Package (Bottom View) 48 Pin LLP (SQA48A) Package Performance Grade Packing 800 fs 2500 Unit Tape and Reel 800 fs 1000 Unit Tape and Reel ...
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