nb3n3001 ON Semiconductor, nb3n3001 Datasheet - Page 7

• Manufacturer Part Number: nb3n3001
• Description: 3.3 V 106.25 Mhz/ 212.5 Mhz Pureedge Clock Generator With Lvpecl Differential Output
• Manufacturer: ON Semiconductor

PC Board Layout Example
NB3N3001. There exists many different potential board
layouts and the one pictured is but one. The crystal X1
footprint shown in this example allows installation of either
surface mount HC49S or through−hole HC49 package. The
footprints of other components in this example are listed in
Table 11. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located
as close as possible to the power pins. The layout assumes
that the board has clean analog power ground plane. The
important aspect of the layout in Figure 11 is the low
impedance connections between V
bypass capacitors. Combining good quality general purpose
chip capacitors with good PCB layout techniques will
produce effective capacitor resonances at frequencies
adequate to supply the instantaneous switching current for
the NB3N3001 outputs. It is imperative that low inductance
chip capacitors are used. It is equally important that the
board layout not introduce any of the inductance saved by
using the leadless capacitors. Thin interconnect traces
between the capacitor and the power plane should be
avoided and multiple large vias should be used to tie the
capacitors to the buried power planes. Fat interconnect and
large vias will help to minimize layout induced inductance
and thus maximize the series resonant point of the bypass
capacitors.
small. It is imperative that no actively switching signals
cross under the crystal as crosstalk energy coupled to these
lines could significantly impact the jitter of the device.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
ORDERING INFORMATION
Specifications Brochure, BRD8011/D.
Figure 11 shows a representative board layout for the
The voltage amplitude across the crystal is relatively
NB3N3001DTG
NB3N3001DTR2G
Device
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Figure 12. Typical Termination for Output Driver and Device Evaluation
Driver
Device
CC
Q
Q
and GND for the
Z
Z
http://onsemi.com
o
o
= 50 W
= 50 W
NB3N3001
TSSOP8 4.4 mm
TSSOP8 4.4 mm
50 W
V
7
(Pb−Free)
(Pb−Free)
TT
Package
= V
Table 11. Footprint Table
Reference
C1, C2
C3
C4, C5
R2
V
CC
TT
− 2.0 V
50 W
Figure 11. PC Board Layout
D
D
Receiver
Device
2500 / Tape & Reel
100 Units / Rail
Shipping
0402
0805
0603
0603
Size
†
C2
C1