nb4l52 ON Semiconductor, nb4l52 Datasheet

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nb4l52

Manufacturer Part Number
nb4l52
Description
2.5 V/3.3 V/5.0 V Differential Data/clock D Flip-flop With Reset Multi-level Inputs To Lvpecl Translator W/ Internal Termination
Manufacturer
ON Semiconductor
Datasheet

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NB4L52
2.5 V/3.3 V/5.0 V Differential
Data/Clock D Flip−Flop
with Reset
Multi−Level Inputs to LVPECL Translator
w/ Internal Termination
differential asynchronous Reset. The differential inputs incorporate
internal 50 W termination resistors and will accept PECL, LVPECL,
LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock
transitions from Low to High, Data will be transferred to the
differential LVPECL outputs. The differential Clock inputs allow the
NB4L52 to also be used as a negative edge triggered device. The
device is housed in a small 3x3 mm 16 pin QFN package.
Features
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2007
January, 2007 − Rev. 2
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
The NB4L52 is a differential Data and Clock D flip−flop with a
LVEP, EP, and SG Devices
Maximum Input Clock Frequency > 4 GHz Typical
330 ps Typical Propagation Delay
145 ps Typical Rise and Fall Times
Differential LVPECL Outputs, 750 mV Peak−to−Peak, Typical
Operating Range: V
Internal Input Termination Resistors, 50 W
Functionally Compatible with Existing 2.5 V/3.3 V/5.0 V LVEL,
−40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices*
CC
= 2.375 V to 5.5 V with V
EE
= 0 V
1
Table 1. TRUTH TABLE
Z = LOW to HIGH Transition
x = Don’t Care
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
*For additional marking information, refer to
Application Note AND8002/D.
R
H
CASE 485G
L
L
MN SUFFIX
(Note: Microdot may be in either location)
VTCLK
VTCLK
QFN−16
VTD
VTD
CLK
CLK
1
ORDERING INFORMATION
Figure 1. Logic Diagram
D
D
A
L
Y
W
G
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
D
H
x
L
VTR R
Data
Clock
MARKING DIAGRAM*
Publication Order Number:
1
Reset
CLK
16
Z
Z
x
R
ALYWG
NB4L
VTR
52
G
NB4L52/D
Q
H
L
L
Q
Q

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nb4l52 Summary of contents

Page 1

... LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock transitions from Low to High, Data will be transferred to the differential LVPECL outputs. The differential Clock inputs allow the NB4L52 to also be used as a negative edge triggered device. The device is housed in a small 3x3 mm 16 pin QFN package. Features • ...

Page 2

... In the differential configuration when the input termination pin (VTD, VTD, VTR, VTR, VTCLK, VTCLK) are connected to a common termination voltage or left open, and if no signal is applied on D/D,CLK/CLK,R/R input then the device will be susceptible to self−oscillation NB4L52 CLK CLK V TCLK TCLK Exposed Pad (EP) Figure 2 ...

Page 3

Table 3. ATTRIBUTES ESD Protection Moisture Sensitivity (Note 2) Flammability Rating Oxygen Index Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol ...

Page 4

Table 5. DC CHARACTERISTICS, CLOCK INPUTS, LVPECL OUTPUTS (V = 2.375 Symbol Characteristic I Power Supply Current (Inputs and Outputs Open Output HIGH Voltage (Note ...

Page 5

Table 6. AC CHARACTERISTICS V CC Symbol Characteristic V Output Voltage Amplitude (@ V OUTPP (Note 10) (See Figure Propagation Delay to PLH t Output Differential PHL t Setup Time s t Hold Time h t Reset ...

Page 6

CLK/D CLK/D Figure 4. Differential Input Driven Single−Ended Figure 6. Differential Inputs Driven Differentially IHmax V thmax V ILmax CLK IHmin V thmin V CLK ILmin ...

Page 7

... ORDERING INFORMATION Device Package NB4L52MNG QFN−16 (Pb−Free) NB4L52MNR2G QFN−16 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes ...

Page 8

... CONDITION CAN NOT VIOLATE 0.2 MM max MINIMUM SPACING BETWEEN LEAD TIP AND FLAG MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF b 0.18 0.30 D 3.00 BSC D2 1.65 1.85 E 3.00 BSC E2 1.65 1.85 e 0.50 BSC K 0.18 TYP L 0.30 0.50 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB4L52/D ...

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