nb4l339 ON Semiconductor, nb4l339 Datasheet - Page 8

• Manufacturer Part Number: nb4l339
• Description: 3.3v 1 4 Clock Fanout Buffer
• Manufacturer: ON Semiconductor

on the first falling edge of CLK after its assertion. The
internal divider flip−flops will maintain their state during the
freeze. When EN is deasserted (LOW), and after the next
Q (÷n)
The EN signal will “freeze” the internal divider flip−flops
CLK
MR
MR
Q (÷1)
Q (÷2)
Q (÷4)
Q (÷8)
CLK
NOTE: On the rising edge of MR, Q goes HIGH after the first rising edge of CLK, following a high−to−low clock transition.
Q (÷n)
CLK
EN
Figure 8. Output Enable Timing Diagrams
t
RR
Figure 7. Master Reset Timing Diagram
Figure 6. Timing Diagram
http://onsemi.com
Internal Clock
Disabled
8
falling edge of CLK, then the internal divider flip−flops will
“unfreeze” and continue to their next state count with proper
phase relationships.
Internal Clock
Enabled
t
RR