nb7l111m ON Semiconductor, nb7l111m Datasheet - Page 11

• Manufacturer Part Number: nb7l111m
• Description: 2.5v / 3.3v, 6.125gb/s 1 10 Differential Clock/data Driver With Cml Output
• Manufacturer: ON Semiconductor

Application Information
LVCMOS and LVDS signal levels. The limitations for
differential input signal (LVDS, PECL, or CML) are
All NB7L111M inputs can accept PECL, CML, LVTTL,
Recommended R
5.0 V 290 W
3.3 V 150 W
2.5 V 80 W
V
CC
R
T
T
Values
PECL
Driver
Driver
LVDS
V
V
V
V
50 W
EE
EE
V
CC
CC
NB7L111M
EE
CML
V
or
CC
Figure 19. PECL to CML Receiver Interface
Figure 20. LVDS to CML Receiver Interface
*V
50 W
BIAS
R
V
Figure 18. CML to CML Interface
T
EE
Q
is within V
R
Q
T
50 W
50 W
http://onsemi.com
CMR
NB7L111M
Z
Z
Range.
Z
Z
11
Z
Z
minimum input swing of 100 mV and the maximum input
swing of 450 mV. Within these conditions, the input voltage
can range from V
illustrated below in a 50 W environment (Z = 50 W).
V
V
BIAS
BIAS
V
V
CC
CC
*
*
V
V
V
V
V
V
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
CLK
CLK
CLK
CLK
CLK
CLK
CC
to 1.2 V. Examples interfaces are
50 W
50 W
V
V
V
50 W
50 W
50 W
50 W
EE
EE
EE
V
V
V
NB7L111M
CC
CC
CC
NB7L111M
NB7L111M
CML
or