nb7l11m ON Semiconductor, nb7l11m Datasheet - Page 2

• Manufacturer Part Number: nb7l11m
• Description: 2.5v/3.3v Differential 1 2 Clock/data Fanout Buffer/ Translator With Cml Outputs And Internal Termination
• Manufacturer: ON Semiconductor

1. In the differential configuration when the input termination pins (V
2. CML outputs require 50 W receiver termination resistor to V
Table 1. PIN DESCRIPTION
9,10,11,12
and if no signal is applied on CLK and CLK then the device will be susceptible to self−oscillation.
5,8,13,16
Pin
14
15
1
2
3
4
6
7
−
Name
V
V
CLK
CLK
V
V
TCLK
TCLK
Q1
Q1
Q0
Q0
EP
CC
EE
LVCMOS, LVTTL,
LVCMOS, LVTTL,
LVPECL, CML,
LVPECL, CML,
CML Output
CML Output
CML Output
CML Output
LVDS
LVDS
I/O
−
−
−
−
−
V
V
TCLK
TCLK
CLK
CLK
Figure 2. QFN−16 Pinout (Top View)
Internal 50 W Termination Pin for CLK
Inverted Differential Clock/Data Input. (Note 1)
Noninverted Differential Clock/Data Input. (Note 1)
Internal 50 W Termination Pin for CLK
Positive Supply Voltage. All V
to guarantee proper operation.
Inverted CLK output 1 with internal 50 W source termination resistor. (Note 2)
Noninverted CLK output 1 with internal 50 W source termination resistor. (Note 2)
Negative Supply Voltage. All V
to guarantee proper operation.
Inverted CLK output 0 with internal 50 W source termination resistor. (Note 2)
Noninverted CLK output 0 with internal 50 W source termination resistor. (Note 2)
Exposed Pad. The thermally exposed pad on package bottom (see case drawing) must
be attached to a heatsinking conduit. It is recommended to connect the EP to the lower
potential (V
1
2
3
4
V
V
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16
CC
5
CC
EE
CC
).
Q0
NB7L11M
15
Q1
for proper operation.
6
TCLK
2
Q1
, V
Q0
14
7
TCLK
V
V
13
8
) are connected to a common termination voltage or left open,
CC
CC
CC
EE
pins must be externally connected to a Power Supply
pins must be externally connected to a Power Supply
Exposed Pad (EP)
12
10
11
9
Description
V
V
V
V
EE
EE
EE
EE