nb7l572 ON Semiconductor, nb7l572 Datasheet - Page 6

• Manufacturer Part Number: nb7l572
• Description: 2.5v / 3.3v Differential 4 1 Mux Input To 1 2 Lvpecl Clock/data Fanout / Translator
• Manufacturer: ON Semiconductor

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
11. Measured using a 100 mVpk−pk source, 50% duty cycle clock source. All output loading with external 50 W to V
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Additive Peak−to−Peak data dependent jitter with input NRZ data at K28.5.
16. Input voltage swing is a single−ended measurement operating in differential mode.
Table 6. AC CHARACTERISTICS
f
f
V
t
t
t
t
t
t
V
t
MAX
DATAMAX
PLH
PHL
PD Tempco
skew
DC
JITTER
r,
Symbol
OUTPP
INPP
, t
rates 40 ps (20% − 80%).
the delays are measured from cross−point of the inputs to the cross−point of the outputs.
f
,
800
750
700
650
600
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
0
(V
Maximum Input Clock Frequency V
Maximum Operating Data Rate NRZ, (PRBS23)
Output Voltage Amplitude (@ V
(Note 12)
Propagation Delay to Differential Outputs
Measured at Differential Cross−Point
Differential Propagation Delay Temperature Coefficient
Output – Output skew (within device) (Note 13)
Device – Device skew (tpd max – tpd min)
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
Additive Random Clock Jitter, RJ(RMS) (Note 14)
Data Dependent Jitter, DDJ (Note 15)
Input Voltage Swing (Differential Configuration) (Note 16)
Output Rise/Fall Times @ 1 GHz; (20% − 80%), V
OUTPP
Figure 2. CLOCK Output Voltage Amplitude
1
fin, CLOCK INPUT FREQUENCY (GHz)
) / RMS Jitter vs. Input Frequency (f
Ambient Temperature (typical)
2
3
V
4
CC
= 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 11)
INPPmin
5
OUT
Characteristic
) (Figure 2 & 9)
w 400 mV
6
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7
@ 1 GHz INx/INx to Qx/Qx (Figure 9)
@ 50 MHz SELx to Qx (Figure 10)
IN
in
) at
= 800 mV Q, Q
6
8
f
f
in
in
f
f
in
in
= 5.0 GHz
= 7.0 GHz
6.5 Gbps
10 Gbps
≤ 5 GHz
≤ 7 GHz
V
INx
INx
Tx
50 W
50 W
Figure 3. Input Structure
10.7
Min
550
215
100
100
45
35
7
V
CC
Typ
750
115
0.5
0.5
50
60
0
CC
− 2 V. Input edge
1200
Max
390
500
100
110
0.8
0.8
15
55
15
15
ps pk−pk
ps rms
Gbps
fs/°C
Unit
GHz
mV
mV
ps
ps
ps
%