nb100lvep224 ON Semiconductor, nb100lvep224 Datasheet - Page 5
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nb100lvep224
Manufacturer Part Number
nb100lvep224
Description
2.5v/3.3v 1 24 Differential Ecl/pecl Clock Driver With Clock Select And Output Enable
Manufacturer
ON Semiconductor
Datasheet
1.NB100LVEP224.pdf
(10 pages)
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NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
11. Input and output parameters vary 1:1 with V
12. All outputs loaded with 50 W to V
13. Single ended input operation is limited V
14. V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
15. Measured with PECL 750 mV source, 50% duty cycle clock source. All outputs loaded with 50 W to V
16. Skew is measured between outputs under identical transitions and conditions on any one device.
17. Device−to−Device skew for identical transitions at identical V
18. OE Set Up Time is defined with respect to the falling edge of the clock. OE High−to−Low transition ensures outputs remain disabled during
19. V
Table 7. NECL DC CHARACTERISTICS
Symbol
Table 8. AC CHARACTERISTICS
Symbol
I
V
V
V
V
V
I
I
V
t
t
t
t
V
t
t
t
EE
IH
IL
PLH
PHL
skew
JITTER
S
H
r
/t
OH
OL
IH
IL
IHCMR
Opp
PP
input signal.
the next clock cycle. OE Low−to−High transition enables normal operation of the next input clock.
f
IHCMR
PP
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
is the differential input voltage swing required to maintain AC characteristics including t
min varies 1:1 with V
Power Supply Current
Output HIGH Voltage (Note 12)
Output LOW Voltage (Note 12)
Input HIGH Voltage (Single−Ended)
(Note 13)
Input LOW Voltage (Single−Ended)
(Note 13)
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 14) (Figure 5)
Input HIGH Current
Input LOW Current
Differential Output Voltage
(Figure 3)
Propagation Delay (Differential Configuration)
Within−Device Skew (Note 16)
Device−to−Device Skew (Note 17)
Random Clock Jitter (Figure 3) (RMS)
Input Swing (Differential Configuration)
(Note 19) (Figure 5)
OE Set Up Time (Note 18)
OE Hold Time
Output Rise/Fall Time
(20%−80%)
Characteristic
Characteristic
EE
, V
CC
IHCMR
V
V
− 2.0 V.
EE
EE
V
CC
max varies 1:1 with V
= −2.5 V
= −3.3 V
EE
CLK_SELx−Qx
= 2.375 V to 3.8 V; V
f
f
f
out
out
≤ −3.0 V in NECL mode.
out
CLK
CLK
CC
V
CC
< 0.8 GHz
< 1.0 GHz
.
< 50 MHz
CLKx−Qx
= 0 V, V
−1945
−1945
−1145
−1165
−150
Min
130
140
0.5
V
EE
http://onsemi.com
EE
+ 1.2
−40°C
−1020
−1820
Min
600
600
600
500
600
200
200
200
100
CC
= −2.375 V to −3.8 V (Note 11)
Typ
160
165
CC
. The V
EE
levels.
5
= 0 V (Note 15)
−405C
Typ
750
750
700
600
700
800
200
−1600
−1600
20
50
−895
−880
1
Max
195
195
150
IHCMR
0.0
1200
Max
700
800
300
300
40
range is referenced to the most positive side of the differential
5
−1145
−1945
−1165
−1945
−150
Min
135
145
0.5
V
EE
Min
600
600
525
550
650
200
200
200
100
+ 1.2
−1020
−1820
25°C
Typ
165
175
255C
Typ
725
725
650
650
800
800
200
20
50
PD
1
−1600
−1600
and device−to−device skew.
−895
−880
Max
200
205
150
0.0
1200
Max
750
900
300
300
40
5
CC
−1945
−1945
−1145
−1165
−150
Min
140
145
− 2 V.
0.5
V
Min
575
550
400
650
750
200
200
200
150
EE
+ 1.2
−1020
−1820
85°C
Typ
165
175
855C
Typ
700
650
525
750
850
100
800
250
35
1
−1600
−1600
1000
1200
1150
−895
−880
Max
Max
300
350
205
210
150
0.0
60
5
Unit
Unit
mV
mV
mV
mV
mA
mV
mV
mV
mV
mA
mA
ps
ps
ps
ps
ps
ps
ps
ps
V