nbsg16m ON Semiconductor, nbsg16m Datasheet - Page 2

• Manufacturer Part Number: nbsg16m
• Description: 2.5v/3.3v Multilevel Input To Cml Clock/data Receiver/driver/translator Buffer
• Manufacturer: ON Semiconductor

Á Á Á
Á Á Á
1. The NC pins are electrically connected to the die and MUST be left open.
2. CML outputs require 50 W receiver termination resistor to V
3. In the differential configuration when the input termination pin (V
Table 1. PIN DESCRIPTION
Pin
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
−
is applied then the device will be susceptible to self−oscillation.
Á Á Á
Á Á Á
Name
V
V
V
V
V
V
V
V
V
V
V
NC
EP
Q
Q
D
D
CC
CC
CC
CC
TD
TD
EE
EE
EE
EE
BB
LVDS, CML, ECL, LVTTL,
LVDS, CML, ECL, LVTTL,
LVCMOS Input
LVCMOS Input
CML Output
CML Output
I/O
−
−
−
−
−
−
−
−
−
−
−
−
−
VTD
VTD
Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á
Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á
D
D
Internal 50 W Termination Pin. See Table 2. (Note 3)
Inverted Differential Input (Note 3)
Noninverted Differential Input. (Note 3)
Internal 50 W Termination Pin. See Table 2. (Note 3)
Positive Supply Voltage. All V
antee proper operation.
No Connect (Note 1)
Negative Supply Voltage. All V
antee proper operation.
Negative Supply Voltage. All V
antee proper operation.
Positive Supply Voltage. All V
antee proper operation.
Noninverted CML Differential Output with Internal 50 W Source Termination Resistor. (Note 2)
Inverted CML Differential Output with Internal 50 W Source Termination Resistor. (Note 2)
Positive Supply Voltage. All V
antee proper operation.
Negative Supply Voltage. All V
antee proper operation.
Negative Supply Voltage. All V
antee proper operation.
Internally Generated ECL Reference Output Voltage
Positive Supply Voltage. All V
antee proper operation.
The Exposed Pad (EP) and the QFN−16 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a heat−
sinking conduit. The pad is not electrically connected to the die but may be electrically and
thermally connected to V
1
2
3
4
Figure 1. QFN−16 Pinout (Top View)
V
V
16
CC
CC
5
V
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NBSG16M
NC V
15
BB
6
CC
V
for proper operation.
14
7
EE
TD
EE
2
, V
EE
V
V
TD
13
8
on the PC board.
EE
EE
) are connected to a common termination voltage, and if no signal
CC
CC
CC
CC
EE
EE
EE
EE
pins must be externally connected to Power Supply to guar-
pins must be externally connected to Power Supply to guar-
pins must be externally connected to Power Supply to guar-
pins must be externally connected to Power Supply to guar-
pins must be externally connected to Power Supply to guar-
pins must be externally connected to Power Supply to guar-
pins must be externally connected to Power Supply to guar-
pins must be externally connected to Power Supply to guar-
12
11
10
9
V
Q
Q
V
Description
CC
CC
Exposed Pad (EP)