74hct2g00 NXP Semiconductors, 74hct2g00 Datasheet
74hct2g00
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74hct2g00 Summary of contents
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... Dual 2-input NAND gate Rev. 04 — 3 July 2008 1. General description The 74HC2G00 and 74HCT2G00 are high-speed Si-gate CMOS devices. They provide two 2-input NAND gates. The HC device has CMOS input switching levels and supply voltage range The HCT device has TTL input switching levels and supply voltage range 4 5.5 V. ...
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... Pinning information 6.1 Pinning 74HC2G00 74HCT2G00 GND 001aai255 Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 74HC_HCT2G00_4 Product data sheet 74HC2G00; 74HCT2G00 Marking code H00 T00 H00 T00 H00 T00 1 & & mna713 Fig 2. IEC logic symbol ...
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... For TSSOP8 package: above 55 C the value of P For VSSOP8 package: above 110 C the value of P For XSON8 package: above 45 C the value of P 74HC_HCT2G00_4 Product data sheet 74HC2G00; 74HCT2G00 Description data input data input ground (0 V) data output supply voltage ...
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... V HIGH-level input IH voltage V LOW-level input IL voltage V HIGH-level output OH voltage V LOW-level output OL voltage I input leakage current I I supply current CC C input capacitance I 74HC_HCT2G00_4 Product data sheet 74HC2G00; 74HCT2G00 Conditions Min Conditions ...
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... V CC per input [1] Figure [2] Figure [3] CC Rev. 04 — 3 July 2008 74HC2G00; 74HCT2G00 Dual 2-input NAND gate = 25 C. amb + +125 C Min Typ Max Min 2.0 1.6 - 2.0 - 1.2 0.8 - 4.4 4.5 - 4.4 4.13 4. ...
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... GND t PHL output THL Table 9. Input 1.3 V Rev. 04 — 3 July 2008 74HC2G00; 74HCT2G00 Dual 2-input NAND gate = 25 C; for test circuit see amb + +125 C Unit Min Typ Max Min - ...
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... DUT R T 10. Load Rev. 04 — 3 July 2008 74HC2G00; 74HCT2G00 Dual 2-input NAND gate open C L 001aad983 of the pulse generator position ...
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... Product data sheet 2.5 scale (1) ( 0.38 0.18 3.1 3.1 0.65 0.22 0.08 2.9 2.9 REFERENCES JEDEC JEITA - - - Rev. 04 — 3 July 2008 74HC2G00; 74HCT2G00 Dual 2-input NAND gate detail 4.1 0.47 0.5 0.2 0.13 0.1 3.9 0.33 EUROPEAN PROJECTION SOT505 ...
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... Product data sheet 2.5 scale (1) ( 0.27 0.23 2.1 2.4 0.5 0.17 0.08 1.9 2.2 REFERENCES JEDEC JEITA MO-187 Rev. 04 — 3 July 2008 74HC2G00; 74HCT2G00 Dual 2-input NAND gate detail 3.2 0.40 0.21 0.4 0.2 0.13 0.15 0.19 3.0 EUROPEAN PROJECTION SOT765-1 v ...
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... 3.1 0.5 0.15 0.6 0.5 1.5 2.9 0.3 0.4 0.05 REFERENCES JEDEC JEITA - - - Rev. 04 — 3 July 2008 74HC2G00; 74HCT2G00 Dual 2-input NAND gate detail 0.1 0.05 0.05 0.1 EUROPEAN PROJECTION SOT996-2 ISSUE DATE 07-12-18 07-12-21 © NXP B.V. 2008. All rights reserved ...
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... The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added type number 74HC2G00GD and 74HCT2G00GD (XSON8U package) 74HC_HCT2G00_3 20060405 74HC_HCT2G00_2 20030212 ...
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... For more information, please visit: For sales office addresses, please send an email to: 74HC_HCT2G00_4 Product data sheet 74HC2G00; 74HCT2G00 [3] Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. ...
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... Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 17 Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 74HC2G00; 74HCT2G00 Dual 2-input NAND gate Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp ...