mk2059-01 Integrated Device Technology, mk2059-01 Datasheet - Page 5

• Manufacturer Part Number: mk2059-01
• Description: Vcxo-based Frame Clock Frequency Translator
• Manufacturer: Integrated Device Technology

A “normalized” PLL loop bandwidth may be calculated as
follows:
The “normalized” bandwidth equation above does not take
into account the effects of damping factor or the second
pole. However, it does provide a useful approximation of
filter performance.
The loop damping factor is calculated as follows:
Where:
As a general rule, the following relationship should be
maintained between components C
filter:
Charge Pump Current Table
IDT™ / ICS™ VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR 5
MK2059-01
VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
NBW
Damping Factor
C
P
1.4 MΩ
680 kΩ
540 kΩ
120 kΩ
R
I
C
=
CP
R
Z
1
(refer to Charge Pump Current Table, below)
SET
=
= Value of capacitor C
C
----- -
= Value of resistor in loop filter (Ohms)
20
= Charge pump current (amps)
N = Crystal multiplier shown in the above table
R
---------------------------------------
S
S
×
Charge Pump Current
I
CP
N
×
=
575
R
100 µA
10 µA
20 µA
25 µA
(I
S
CP
×
)
---------------------------------------- -
625
1
in loop filter (Farads)
1
×
and C
I
N
CP
×
2
C
in the loop
S
Special considerations must be made in choosing loop
components C
found on the ICS web site.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω. (The
optional series termination resistor is not shown in the
External Component Schematic.)
Decoupling Capacitors
As with any high performance mixed-signal IC, the
MK2059-01 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To further
guard against interfering system supply noise, the
MK2059-01 should use one common connection to the PCB
power plane as shown in the diagram on the next page. The
ferrite bead and bulk capacitor help reduce lower frequency
noise in the supply that can lead to output clock phase
modulation.
Recommended Power Supply Connection for
Optimal Device Performance
B ulk D ecoupling C apacitor
C onnection to 3.3V
(such as 1 F Tantalum )
0.01
P ow er P lane
S
F D ecoupling C apacitors
and C
P
. These recommendations can be
Ferrite
Bead
VCXO AND SYNTHESIZER
MK2059-01
V D D P in
V D D P in
V D D P in
REV F 030106