mc145480vf Freescale Semiconductor, Inc, mc145480vf Datasheet - Page 7

• Manufacturer Part Number: mc145480vf
• Description: Mc145480 5 V Pcm Codec-filter
• Manufacturer: Freescale Semiconductor, Inc

Long Frame Sync
clocking format that controls the transfer of the PCM data
words. (Refer to Figure NO TAGa.) The ‘‘Frame Sync’’ or
‘‘Enable’’ is used for two specific synchronizing functions.
The first is to synchronize the PCM data word transfer, and
the second is to control the internal analog–to–digital and
digital–to–analog conversions. The term ‘‘Sync’’ refers to the
function of synchronizing the PCM data word onto or off of
the multiplexed serial PCM data bus, which is also known as
a PCM highway. The term ‘‘Long’’ comes from the duration of
the frame sync measured in PCM data clock cycles. Long
Frame Sync timing occurs when the frame sync is used di-
rectly as the PCM data output driver enable. This results in
the PCM output going low impedance with the rising edge of
the transmit frame sync, and remaining low impedance for
the duration of the transmit frame sync.
compatibility and been optimized for external clocking sim-
plicity. This optimization includes the PCM data output going
low impedance with the logical AND of the transmit frame
sync (FST) with the transmit data bit clock (BCLKT). The op-
timization also includes the PCM data output (DT) remaining
low impedance until the middle of the LSB (seven and a half
PCM data clock cycles) or until the FST pin is taken low,
whichever occurs last. This requires the frame sync to be
approximately rising edge aligned with the initiation of the
PCM data word transfer, but the frame sync does not have a
precise timing requirement for the end of the PCM data word
transfer. The device recognizes Long Frame Sync clocking
when the frame sync is held high for two consecutive falling
edges of the transmit data clock. The transmit logic decides
on each frame sync whether it should interpret the next
frame sync pulse as a Long or a Short Frame Sync. This de-
cision is used for receive circuitry also. The device is de-
signed to prevent PCM bus contention by not allowing the
PCM data output to go low impedance for at least two frame
sync cycles after power is applied or when coming out of the
powered down mode.
same frame sync and data clock as the transmit side and to
be able to latch its own transmit PCM data word. Thus the
PCM digital switch needs to be able to generate only one
type of frame sync for use by both transmit and receive sec-
tions of the device.
data clock tells the device to start latching the 8–bit serial
word into the receive data input on the falling edges of the
receive data clock. The internal receive logic counts the re-
ceive data clock cycles and transfers the PCM data word to
the digital–to–analog converter sequencer on the ninth data
clock rising edge.
To ensure that this device does not reprogram itself for a dif-
ferent timing mode, the BCLKR pin must change logic state
no less than every 125 s. The minimum PCM data bit clock
frequency of 64 kHz satisfies this requirement.
Short Frame Sync
clocking format that controls the transfer of the PCM data
words (refer to Figure NO TAGb). The ‘‘Frame Sync’’ or ‘‘En-
MOTOROLA
Long Frame Sync is the industry name for one type of
The implementation of Long Frame Sync has maintained
The receive side of the device is designed to accept the
The logical AND of the receive frame sync with the receive
This device is compatible with four digital interface modes.
Short Frame Sync is the industry name for the type of
able’’ is used for two specific synchronizing functions. The
first is to synchronize the PCM data word transfer, and the
second is to control the internal analog–to–digital and digital–
to–analog conversions. The term ‘‘Sync’’ refers to the func-
tion of synchronizing the PCM data word onto or off of the
multiplexed serial PCM data bus, which is also known as a
PCM highway. The term ‘‘Short’’ comes from the duration of
the frame sync measured in PCM data clock cycles. Short
Frame Sync timing occurs when the frame sync is used as a
‘‘pre–synchronization’’ pulse that is used to tell the internal
logic to clock out the PCM data word under complete control
of the data clock. The Short Frame Sync is held high for one
falling data clock edge. The device outputs the PCM data
word beginning with the following rising edge of the data
clock. This results in the PCM output going low impedance
with the rising edge of the transmit data clock, and remaining
low impedance until the middle of the LSB (seven and a half
PCM data clock cycles).
the frame sync is held high for one and only one falling edge
of the transmit data clock. The transmit logic decides on each
frame sync whether it should interpret the next frame sync
pulse as a Long or a Short Frame Sync. This decision is used
for receive circuitry also. The device is designed to prevent
PCM bus contention by not allowing the PCM data output to
go low impedance for at least two frame sync cycles after
power is applied or when coming out of the powered down
mode.
same frame sync and data clock as the transmit side and to
be able to latch its own transmit PCM data word. Thus the
PCM digital switch needs to be able to generate only one
type of frame sync for use by both transmit and receive sec-
tions of the device.
logic level at the receive frame sync input tells the device to
start latching the 8–bit serial word into the receive data input
on the following eight falling edges of the receive data clock.
The internal receive logic counts the receive data clock
cycles and transfers the PCM data word to the digital–to–
analog converter sequencer on the rising data clock edge af-
ter the LSB has been latched into the device.
To ensure that this device does not reprogram itself for a dif-
ferent timing mode, the BCLKR pin must change logic state
no less than every 125 s. The minimum PCM data bit clock
frequency of 64 kHz satisfies this requirement.
Interchip Digital Link (IDL)
standard synchronous 2B+D ISDN timing interface modes
with which this device is compatible. In the IDL mode, the de-
vice can communicate in either of the two 64 kbps B chan-
nels (refer to Figure NO TAGc for sample timing). The IDL
mode is selected when the BCLKR pin is held high for two or
more FST (IDL SYNC) rising edges. The digital pins that con-
trol the transmit and receive PCM word transfers are repro-
grammed to accommodate this mode. The pins affected are
FST, FSR, BCLKT, DT, and DR. The IDL Interface consists of
four pins: IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (DT),
and IDL RX (DR). The IDL interface mode provides access to
both the transmit and receive PCM data words with common
control clocks of IDL Sync and IDL Clock. In this mode, the
The device recognizes Short Frame Sync clocking when
The receive side of the device is designed to accept the
The falling edge of the receive data clock latching a high
This device is compatible with four digital interface modes.
The Interchip Digital Link (IDL) Interface is one of two
MC145480
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