mc145053p Lansdale Semiconductor, Inc., mc145053p Datasheet - Page 7

• Manufacturer Part Number: mc145053p
• Description: 10-bit A/d Converter With Serial Interface Cmos
• Manufacturer: Lansdale Semiconductor, Inc.

ML145053
on the first four rising edges of SCLK, and the previous 10-bit
conversion result is shifted out on the first nine falling edges
of SCLK. After the fourth rising edge of SCLK, the new mux
address is available; therefore, on the next edge of SCLK (the
fourth falling edge), the analog input voltage on the selected
mux input begins charging the RC DAC and continues to do so
until the tenth falling edge of SCLK. After this tenth SCLK
edge, the analog input voltage is disabled from the RC DAC
and the RC DAC begins the “hold” portion of the A/D conver-
sion sequence. Also upon this tenth SCLK edge, control of the
internal circuitry is transferred to the internal clock oscillator
which drives the successive approximation logic to complete
the conversion. If 16 SCLK cycles are used during each trans-
fer, then there is a constraint on the minimum SCLK frequen-
cy. Specifically, there must be at least one rising edge on
SCLK before the A/D conversion is complete. If the SCLK
frequency is too low and a rising edge does not occur during
the conversion, the chip is thrown out of sync with the proces-
sor and CS needs to be toggled in order to restore proper oper-
ation. If 10 SCLKs are used per transfer, then there is no lower
frequency limit on SCLK. Also note that if the ADC is operat-
ed such that CS is inactive high between transfers, then the
number of SCLK cycles per transfer can be anything between
10 and 16 cycles, but the “rising edge” constraint is still in
effect if more than 10 SCLKs are used. (If CS stays active low
for multiple transfers, the number of SCLK cycles must be
either 10 or 16.)
EOC
End-of-Conversion Output (Pin 1)
high transition on EOC occurs when the A/D conversion is
complete and the data is ready for transfer.
ANALOG INPUTS AND TEST MODES
AN0 through AN4
Analog Multiplexer Inputs (Pins 2 – 6)
address register. AN1 is addressed by $1, AN2 by $2, AN3 by
$3, and AN4 by $4. Table 2 shows the input format for a 16-bit
stream. The mux features a break-before-make switching struc-
ture to minimize noise injection into the analog inputs. The
source resistance driving these inputs must be
normal operation, leakage currents through the analog mux
Page 7 of 15
EOC goes low on the tenth falling edge of SCLK. A low-to-
The input AN0 is addressed by loading $0 into the mux
≤
1 kΩ. During
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from unselected channels to a selected channel and leakage
currents through the ESD protection diodes on the selected
channel occur. These leakage currents cause an offset voltage
to appear across any series source resistance on the selected
channel. Therefore, any source resistance greater than 1 kΩ
(Lansdale test condition) may induce errors in excess of guar-
anteed specifications.There are three tests available that verify
the functionality of all the control logic as well as the succes-
sive approximation comparator. These tests are performed by
addressing $B, $C, or $D and they convert a voltage of (V ref +
V AG )/2, V AG , or V ref , respectively. The voltages are obtained
internally by sampling V ref or V AG onto the appropriate ele-
ments of the RC DAC during the sample phase. Addressing
$B, $C, or $D produces an output of $200 (half scale), $000,
or $3FF (full scale), respectively, if the converter is functioning
properly. However, deviation from these values occurs in the
presence of sufficient system noise (external to the chip)
onV DD , V SS , V ref , or V AG .
POWER AND REFERENCE PINS
V SS and V DD
Device Supply Pins (Pins 7 and 14)
nected to a positive digital supply voltage. Low frequency
(V DD – V SS ) variations over the range of 4.5 to 5.5 volts do
not affect the A/D accuracy. (See the Operations Ranges Table
for restrictions on V ref and V AG relative to V DD and V SS .)
Excessive inductance in the V DD or V SS lines, as on automat-
ic test equipment, may cause A/D offsets > ± 1 LSB. Use of a
0.1 µF bypass capacitor across these pins is recommended.
V AG and V ref
Analog Reference Voltage Pins (Pins 8 and 9)
and upper boundary of the A/D conversion. Analog input volt-
ages ≥ V ref produce a full scale output and input voltages ≤
V AG produce an output of zero. CAUTION: The analog input
voltage must be ≥ V SS and ≤ V DD . The A/D conversion result
is ratiometric to V ref – V AG . V ref and V AG must be as noise-
free as possible to avoid degradation of the A/D conversion.
Ideally, V ref and V AG should be single-point connected to the
voltage supply driving the system's transducers. Use of a 0.22
µF bypass capacitor across these pins is strongly urged.
V SS is normally connected to digital ground; V DD is con-
Analog reference voltage pins which determine the lower
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