74vhc4046 National Semiconductor Corporation, 74vhc4046 Datasheet - Page 10

• Manufacturer Part Number: 74vhc4046
• Description: Cmos Phase Lock Loop
• Manufacturer: National Semiconductor Corporation

Figure 5 shows the state tables for all three comparators
Detailed Circuit Description
Thus in normal operation V
fed to the loop filter This differs from some phase detectors
which supply a current output to the loop filter and this
should be considered in the design (The CD4046 also pro-
vides a voltage )
PHASE COMPARATOR I
This comparator is a simple XOR gate similar to the
54 74HC86 and its operation is similar to an overdriven
balanced modulator To maximize lock range the input fre-
quencies must have a 50% duty cycle Typical input and
output waveforms are shown in Figure 4 The output of the
phase detector feeds the loop filter which averages the out-
put voltage The frequency range upon which the PLL will
lock onto if initially out of lock is defined as the capture
range The capture range for phase detector I is dependent
on the loop filter employed The capture range can be as
large as the lock range which is equal to the VCO frequency
range
To see how the detector operates refer to Figure 4 When
two square wave inputs are applied to this comparator an
output waveform whose duty cycle is dependent on the
phase difference between the two signals results As the
phase difference increases the output duty cycle increases
and the voltage after the loop filter increases Thus in order
to achieve lock when the PLL input frequency increases the
Phase Comparator State Diagrams
CC
and ground voltage levels are
(Continued)
FIGURE 5 PLL State Tables
10
7 shows some typical loop waveforms First assume that
VCO input voltage must increase and the phase difference
between comparator in and signal in will increase At an
input frequency equal f
requires the phase detector output to be ground hence the
two input signals must be in phase When the input frequen-
cy is f
detector inputs must be 180 out of phase
The XOR is more susceptible to locking onto harmonics of
the signal input than the digital phase detector II This can
be seen by noticing that a signal 2 times the VCO frequency
results in the same output duty cycle as a signal equal the
VCO frequency The difference is that the output frequency
of the 2f example is twice that of the other example The
loop filter and the VCO range should be designed to prevent
locking on to harmonics
PHASE COMPARATOR II
This detector is a digital memory network It consists of four
flip-flops and some gating logic a three state output and a
phase pulse output as shown in Figure 6 This comparator
acts only on the positive edges of the input signals and is
thus independent of signal duty cycle
Phase comparator II operates in such a way as to force the
PLL into lock with 0 phase difference between the VCO
output and the signal input positive waveform edges Figure
the signal input phase is leading the comparator input This
max
then the VCO input must be V
min
the VCO input is at 0V and this
TL F 11675 – 21
CC
and the phase