nbc12430 ON Semiconductor, nbc12430 Datasheet

no-image

nbc12430

Manufacturer Part Number
nbc12430
Description
3.3v/5vprogrammable Pll Synthesized Clock Generator
Manufacturer
ON Semiconductor
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
nbc12430AFA
Manufacturer:
ON Semiconductor
Quantity:
10 000
Part Number:
nbc12430AFAG
Manufacturer:
ON Semiconductor
Quantity:
249
Part Number:
nbc12430AFAG
Manufacturer:
ON Semiconductor
Quantity:
10 000
Part Number:
nbc12430AFAR2
Manufacturer:
ON Semiconductor
Quantity:
10 000
Part Number:
nbc12430AFAR2G
Manufacturer:
ON Semiconductor
Quantity:
10 000
Part Number:
nbc12430AFAR2G
Manufacturer:
ON/安森美
Quantity:
20 000
Part Number:
nbc12430AFN
Manufacturer:
ON Semiconductor
Quantity:
10 000
Part Number:
nbc12430AFNG
Manufacturer:
ON Semiconductor
Quantity:
29
Part Number:
nbc12430AFNG
Manufacturer:
ON/安森美
Quantity:
20 000
Part Number:
nbc12430FAG
Manufacturer:
ON
Quantity:
58
Part Number:
nbc12430FAG
Manufacturer:
ON Semiconductor
Quantity:
1
Part Number:
nbc12430FAR2G
Manufacturer:
ON Semiconductor
Quantity:
2 750
Part Number:
nbc12430FAR2G
Manufacturer:
ON/安森美
Quantity:
20 000
NBC12430, NBC12430A
3.3V/5V Programmable PLL
Synthesized Clock
Generator
50 MHz to 800 MHz
synthesized clock sources. The VCO will operate over a frequency
range of 400 MHz to 800 MHz. The VCO frequency is sent to the
N-output divider, where it can be configured to provide division ratios
of 1, 2, 4, or 8. The VCO and output frequency can be programmed
using the parallel or serial interfaces to the configuration logic. Output
frequency steps of 250 KHz, 500 KHz, 1.0 MHz, 2.0 MHz can be
achieved using a 16 MHz crystal, depending on the output dividers
settings. The PLL loop filter is fully integrated and does not require
any external components.
Features
© Semiconductor Components Industries, LLC, 2007
May, 2007 - Rev. 10
The NBC12430 and NBC12430A are general purpose, PLL based
During Powerup
MPC9230
Best-in-Class Output Jitter Performance, ±20 ps Peak-to-Peak
50 MHz to 800 MHz Programmable Differential PECL Outputs
Fully Integrated Phase-Lock-Loop with Internal Loop Filter
Parallel Interface for Programming Counter and Output Dividers
Minimal Frequency Overshoot
Serial 3-Wire Programming Interface
Crystal Oscillator Interface
Operating Range: V
CMOS and TTL Compatible Control Inputs
Pin and Function Compatible with Motorola MC12430 and
0°C to 70°C Ambient Operating Temperature (NBC12430)
-40 °C to 85°C Ambient Operating Temperature (NBC12430A)
Pb-Free Packages are Available
CC
= 3.135 V to 5.25 V
1
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
(Note: Microdot may be in either location)
CASE 488AM
CASE 873A
FA SUFFIX
FN SUFFIX
MN SUFFIX
CASE 776
LQFP-32
PLCC-28
QFN32
1
ORDERING INFORMATION
x
A
WL, L
YY, Y
WW, W = Work Week
G or G
32
http://onsemi.com
= Blank or A
= Assembly Location
= Wafer Lot
= Year
= Pb-Free Package
Publication Order Number:
1
NBC12430xG
DIAGRAMS
AWLYYWWG
AWLYYWW
MARKING
AWLYYWWG
NBC12
NBC12
430x
NBC12430/D
430x
1 28
G

Related parts for nbc12430

nbc12430 Summary of contents

Page 1

... Synthesized Clock Generator 50 MHz to 800 MHz The NBC12430 and NBC12430A are general purpose, PLL based synthesized clock sources. The VCO will operate over a frequency range of 400 MHz to 800 MHz. The VCO frequency is sent to the N-output divider, where it can be configured to provide division ratios ...

Page 2

... COUNTER 10-20MHz OSC 5 XTAL2 S_LOAD 7 P_LOAD 27 S_DATA 26 S_CLOCK Table 1. Output Division N [1:0] Output Division NBC12430, NBC12430A +3 PLL_V REF PHASE DETECTOR VCO ( 400-800 MHz LATCH LATCH BIT SR 9- BIT 17, 18 ...

Page 3

... XTAL1 S_CLOCK 1 S_DATA 2 S_LOAD 3 PLL_V 4 CC PLL_V 5 CC FREF_EXT 6 7 XTAL_SEL XTAL1 Figure 3. 32-Lead QFN (Top View) NBC12430, NBC12430A Figure 2. 28-Lead PLCC (Top View N/C 24 N[1] 23 S_CLOCK N[0] ...

Page 4

... The following gives a brief description of the functionality of the NBC12430 and NBC12430A Inputs and Outputs. Unless explicitly stated, all inputs are CMOS/TTL compatible with either pullup or pulldown resistors. The PECL outputs are capable of driving two series terminated 50 W transmission lines on the incident edge. ...

Page 5

... Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NBC12430, NBC12430A Characteristics Human Body Model ...

Page 6

... T = -40°C to 85°C (NBC12430A Characteristic F OUT F OUT TEST F OUT F OUT TESt V PLL_V variation 2 0°C to 70°C (NBC12430 -40°C to 85°C (NBC12430A Characteristic F OUT F OUT TEST F OUT F OUT TEST V PLL_V variation 2 http://onsemi ...

Page 7

... OUT 100 MHz v f OUT S_DATA to S_CLOCK S_CLOCK to S_LOAD P_LOAD S_DATA to S_CLOCK P_LOAD S_LOAD P_LOAD F 20%-80% OUT - 2 http://onsemi.com 7 = -40°C to 85°C (NBC12430A)) (Note 7) A Min Max 400 800 50 800 10 < 100 MHz 8 < 800 MHz 5 " ...

Page 8

... NBC12430, NBC12430A FUNCTIONAL DESCRIPTION for the output driver and the internal logic is separated from the power supply for the phase-locked loop to minimize noise induced jitter. ...

Page 9

... Programming the NBC12430 and NBC12430A is accomplished by properly configuring the internal dividers to produce the desired frequency at the outputs. The output frequency can by represented by this formula: F OUT + ((F XTAL or F REF_EXT ) B 16) where F is the crystal frequency the loop divider XTAL modulus, and N is the output divider modulus. Note that it is possible to select values of M such that the PLL is unable to achieve loop lock ...

Page 10

... NBC12430, NBC12430A 10 Á Á Á Á 12 Á Á Á 14 Á Á Á 16 Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ...

Page 11

... SHIFT REG T0 14- BIT T1 T2 SLOAD • T2=T1=1, T0=0: Test Mode • SCLOCK is selected, MCNT is on TEST output, SCLOCK PLOAD acts as reset for test pin latch. When latch reset, T2 data is shifted out TEST pin. NBC12430, NBC12430A M[8:0] N[1:0] P_LOAD Figure 5 ...

Page 12

... DC voltage drop that will be seen between the V supply and the PLL_V CC NBC12430A . From the data sheet, the PLL_V (the current sourced through the PLL_V 24 mA (30 mA maximum). Assuming that a minimum of 2.8 V must be maintained on the PLL_V DC voltage drop can be tolerated when a 3 used ...

Page 13

... Figure 9 shows a representative board layout for the NBC12430 and NBC12430A . There exists many different potential board layouts and the one pictured is but one. The important aspect of the layout in Figure 9 is the low impedance connections between V and GND for the bypass capacitors ...

Page 14

... The number of cycles used to look for the maximum jitter varies by application but the JEDEC spec is 10,000 observed cycles. The NBC12430 and NBC12430A exhibit long term and cycle-to-cycle jitter, which rivals that of SAW based oscillators. This jitter performance comes with the added flexibility associated with a synthesizer over a fixed frequency oscillator ...

Page 15

... NBC12430, NBC12430A S_DATA S_CLOCK t SETUP Figure 14. Setup and Hold S_DATA t S_LOAD SETUP Figure 15. Setup and Hold M[8:0] N[1:0] P_ LOAD t SETUP Figure 16. Setup and Hold F OUT F OUT Pulse Width Figure 17. Output Duty Cycle t HOLD t HOLD t HOLD t PERIOD http://onsemi.com 15 tpw DCO + tPERIOD ...

Page 16

... NBC12430AFA NBC12430AFAG NBC12430AFAR2 NBC12430AFAR2G NBC12430AFN NBC12430AFNG NBC12430AFNR2 NBC12430AFNR2G NBC12430AMNG NBC12430AMNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NBC12430, NBC12430A F D OUT F D OUT ...

Page 17

... NBC12430, NBC12430A Resource Reference of Application Notes AN1405/D - ECL Clock Distribution Techniques AN1406/D - Designing with PECL (ECL at +5.0 V) AN1503/D - ECLinPSt I/O SPiCE Modeling Kit AN1504/D - Metastability and the ECLinPS Family AN1568/D - Interfacing Between LVDS and ECL AN1672/D - The ECL Translator Guide AND8001/D - Odd Number Counters Design ...

Page 18

... DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). NBC12430, NBC12430A PACKAGE DIMENSIONS PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E ...

Page 19

... DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. NBC12430, NBC12430A PACKAGE DIMENSIONS 32 LEAD LQFP CASE 873A-02 ISSUE C 4X 0.20 (0.008) AB ...

Page 20

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT:  Literature Distribution Center for ON Semiconductor  P.O. Box 5163, Denver, Colorado 80217 USA  Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada  Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada  Email: orderlit@onsemi.com NBC12430, NBC12430A PACKAGE DIMENSIONS QFN32 5*5*1 0.5 P CASE 488AM-01 ISSUE ...

Related keywords