hsp43881 ETC-unknow, hsp43881 Datasheet - Page 10

• Manufacturer Part Number: hsp43881
• Description: Digital Filter
• Manufacturer: ETC-unknow

Detailed operation of the DF to perform a basic 8-tap, 8-bit
coefficient, 8-bit data, 30MHz FIR filter is best understood by
observing the schematic (Figure 3) and timing diagram
(Figure 4). The internal pipeline length of the DF is four (4)
clock cycles, corresponding to the register levels CREG (or
XREG), MREG0, MREG1, and TREG (Figures 1 and 2).
Therefore, the delay from presentation of data and
coefficients at the DIN0-7 and CIN0-7 inputs to a sum
appearing at the SUM0-25 output is:
k + Td
Where:
k = filter length
Td = 4, the internal pipeline delay of DF
After the pipeline has filled, a new output sample is available
every clock. The delay to last sample output from last
sample input is Td.
The output sums, Yn, shown in the Timing Diagram are
derived from the sum of products equation:
Y(n) = C(0) x X(n) + C(1) x X(n1) + C(2) x X(n -2) + C(3)
x X(n -3) + C(4) x X(n -4) + C(5) x X(n -5) + C(6) x X(n -6)
+ C(7) x X(n -7)
SAMPLE
SYSTEM
DATA IN
CLOCK
ERASE
RESET
30MHz
(X n )
10
A2 A1 A0
8 x 8 COEFF.
Y
FIGURE 3. 30MHZ, 8 TAP FIR FILTER APPLICATION SCHEMATIC
COUNTER
RAM/ROM
2
3-BIT
Y
D0-D7
1
Y
0
8
8
ADR2
DIN0-7
DIENB
TCS
CLK
TCCI
CIN0-7
CIENB
HSP43881
ADR1
DCM1
ADR0
Extended FIR Filter Length
Filter lengths greater that eight taps can be created by either
cascading together multiple DF devices or “reusing” a single
device. Using multiple devices, an FIR filter of over 1000-
taps can be constructed to operate at a 30MHz sample rate.
Using a single device clocked at 30MHz, a FIR filter of over
1000 taps can be constructed to operate at less than a
30MHz sample rate. Combinations of these two techniques
are also possible.
DCM0
V
HSP43881
+5V
RESET
CC
SHADD
ERASE
SENBH
V
SS
SUM0-25
COUT0-7
COENB
SENBL
TCCO
26
8
SUM
OUT
(Y n )
NC
NC