adc12132 National Semiconductor Corporation, adc12132 Datasheet - Page 3

• Manufacturer Part Number: adc12132
• Description: Self-calibrating 12-bit Plus Sign Serial I/o A/d Converters With Mux And Sample/hold
• Manufacturer: National Semiconductor Corporation

Connection Diagrams
Ordering Information
Pin Descriptions
CCLK
SCLK
The clock applied to this input controls the suc-
cessive approximation conversion time interval
and the acquisition time. The rise and fall times
of the clock edges should not exceed 1 µs.
This is the serial data clock input. The clock
applied to this input controls the rate at which
the serial data exchange occurs. The rising
edge loads the information at the DI pin into the
multiplexer address and mode select shift reg-
ister. This address controls which channel of
the analog input multiplexer (MUX) is selected
28-Pin Dual-In-Line, SSOP and
Wide Body SO Packages
* The ADC12132 is obsolete and shown in this document for reference only.
ADC12130CIN
ADC12130CIWM
ADC12130CIWMX
ADC12132CIMSA *
ADC12132CIMSAX *
ADC12138CIN
ADC12138CIWM
ADC12138CIWMX
ADC12138CIMSA
ADC12138CIMSA
Top View
Industrial Temperature Range
−40˚C ≤ T
(Continued)
A
01207903
≤ +85˚C
3
M16B, Wide Body SO - Tape & Reel
MSA20, SSOP - Tape & Reel
MSA28, SSOP - Tape & Reel
NS Package Number
M16B, Wide Body SO
M28B - Tape & Reel
N16E, Dual-In-Line
N28B, Dual-In-Line
MSA20, SSOP
MSA28, SSOP
M28B
and the mode of operation for the A/D. With CS
low, the falling edge of SCLK shifts the data
resulting from the previous ADC conversion out
on DO, with the exception of the first bit of data.
When CS is low continuously, the first bit of the
data is clocked out on the rising edge of EOC
(end of conversion). When CS is toggled, the
falling edge of CS always clocks out the first bit
of data. CS should be brought low when SCLK
is low. The rise and fall times of the clock edges
should not exceed 1 µs.
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