adc12l063civy National Semiconductor Corporation, adc12l063civy Datasheet - Page 16

• Manufacturer Part Number: adc12l063civy
• Description: 12-bit, 62 Msps, 354 Mw A/d Converter With Internal Sample-and-hold
• Manufacturer: National Semiconductor Corporation

www.national.com
Functional Description
Operating on a single +3.3V supply, the ADC12L063 uses a
pipelined architecture and has error correction circuitry to
help ensure maximum performance.
Differential analog input signals are digitized to 12 bits. Each
analog input signal should have a peak-to-peak voltage
equal to the input reference voltage, V
around V
output relationship of the ADC12L063. As indicated in Table
2, biasing one input to V
its full range signal results in a 6 dB reduction of the output
range, limiting it to the range of
output range obtainable if both inputs were driven with com-
plimentary signals. Section 1.3 explains how to avoid this
signal reduction.
The output word rate is the same as the clock frequency,
which can be between 1 MSPS and 70 MSPS (typical). The
analog input voltage is acquired at the rising edge of the
clock and the digital data for that sample is delayed by the
pipeline for 6 clock cycles.
A logic high on the power down (PD) pin reduces the con-
verter power consumption to 50 mW.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC12L063:
1.1 Analog Inputs
The ADC12L063 has two analog signal inputs, V
These two pins form a differential input pair. There is one
reference input pin, V
V
V
V
V
V
V
3.0 V ≤ V
V
1.5V ≤ V
1 MHz ≤ f
0.8V ≤ V
CM
CM
CM
CM
CM
CM
D
V
V
CM
CM
= V
−0.25
+0.25
−0.5
+0.5
−0.5
+0.5
TABLE 1. Input to Output Relationship —
TABLE 2. Input to Output Relationship —
V
V
V
V
REF
−V
+V
IN +
CM
IN +
CM
A
DR
REF
*
*
*
*
*
*
A
REF
REF
CLK
/2. Table 1 and Table 2 indicate the input to the
V
V
V
V
V
V
≤ 3.6V
≤ V
REF
REF
REF
REF
REF
REF
≤ 1.2V
≤ 70 MHz
D
Single-Ended Input
Differential Input
V
V
V
V
REF
CM
CM
CM
CM
REF
.
+0.25
−0.25
+0.5
−0.5
/2 and driving the other input with
V
V
V
V
V
V
V
V
CM
CM
CM
CM
CM
CM
IN −
IN −
*
*
*
*
V
V
V
V
1
REF
REF
REF
REF
⁄
4
to
REF
3
⁄
0000 0000 0000
0100 0000 0000
1000 0000 0000
0000 0000 0000
0100 0000 0000
1000 0000 0000
4
1100 0000 0000
1100 0000 0000
, and be centered
1111 1111 1111
1111 1111 1111
of the minimum
Output
Output
IN +
and V
IN −
.
16
1.2 Reference Pins
The ADC12L063 is designed to operate with a 1.0V refer-
ence, but performs well with reference voltages in the range
of 0.8V to 1.2V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC12L063. Increasing
the reference voltage (and the input signal swing) beyond
1.2V will degrade THD for a full-scale input. It is very impor-
tant that all grounds associated with the reference voltage
and the input signal make connection to the analog ground
plane at a single point to minimize the effects of noise
currents in the ground path.
The three Reference Bypass Pins (V
made available for bypass purposes only. These pins should
each be bypassed to ground with a 0.1 µF capacitor. DO
NOT LOAD these pins.
1.3 Signal Inputs
The signal inputs are V
defined as
Figure 2 shows the expected input signal range.
Note that the nominal input common mode voltage, V
V
between the limits of AGND and 1.0V with V
differential input signal increases above 2 V
input common mode voltage should increase proportionally.
The Peaks of the input signals should never exceed the
voltage described as
to maintain dynamic performance.
The ADC12L063 performs best with a differential input with
each input centered around V
peak-to-peak voltage swing at both V
exceed the value of the reference voltage or the output data
will be clipped. The two input signals should be exactly 180˚
out of phase from each other and of the same amplitude. For
single frequency inputs, angular errors result in a reduction
of the effective full scale input. For a complex waveform,
however, angular errors will result in distortion.
For angular deviations of up to 10 degrees from these two
signals being 180 out of phase, the full scale error in LSB
can be described as approximately
Where dev is the angular difference between the two signals
having a 180˚ relative phase relationship to each other (see
Figure 3). Drive the analog inputs with a source impedance
less than 100Ω.
REF
/2, minimum and the nominal input signals each run
FIGURE 2. Expected Input Signal Range
Peak Input Voltaged = V
V
IN
E
IN +
= (V
FS
and V
= dev
IN +
) – (V
CM
IN −
1.79
. The input signal, V
(minimum of 0.5V). The
IN −
IN +
RP
20026311
A
)
, V
and V
− 1.0
RM
P-P
REF
, the minimum
IN −
and V
= 1.0V. If the
should not
RN
CM
) are
IN
, is
, is