adc12l066civyx National Semiconductor Corporation, adc12l066civyx Datasheet - Page 20

• Manufacturer Part Number: adc12l066civyx
• Description: 12-bit, 66 Msps, 450 Mhz Bandwidth A/d Converter With Internal Sample-and-hold
• Manufacturer: National Semiconductor Corporation

www.national.com
Functional Description
Operating on a single +3.3V supply, the ADC12L066 uses a
pipeline architecture and has error correction circuitry to help
ensure maximum performance.
Differential analog input signals are digitized to 12 bits. Each
analog input signal should have a peak-to-peak voltage
equal to the input reference voltage, V
around a common mode voltage, V
phase with each other. Table 1 and Table 2 indicate the input
to output relationship of the ADC12L066. Biasing one input
to V
results in a 6 dB reduction of the output range, limiting it to
the range of
if both inputs were driven with complimentary signals. Sec-
tion 1.3 explains how to avoid this signal reduction.
The output word rate is the same as the clock frequency,
which can be between 1 MSPS and 80 MSPS (typical). The
analog input voltage is acquired at the rising edge of the
clock and the digital data for that sample is delayed by the
pipeline for 6 clock cycles.
A logic high on the power down (PD) pin reduces the con-
verter power consumption to 50 mW.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC12L066:
0.5V ≤ V
1.1 Analog Inputs
The ADC12L066 has two analog signal inputs, V
V
one reference input pin, V
TABLE 2. Input to Output Relationship–Single-Ended
IN−
3.0 V ≤ V
V
1.8V ≤ V
1 MHz ≤ f
0.8V ≤ V
TABLE 1. Input to Output Relationship–Differential
V
V
V
V
V
V
D
CM
. These two pins form a differential input pair. There is
V
V
CM
CM
CM
CM
CM
CM
CM
CM
= V
and driving the other input with its full range signal
V
V
V
− V
− V
+ V
+ V
V
− V
+ V
CM
−V
+V
A
IN +
CM
IN +
CM
DR
REF
REF
REF
REF
REF
REF
REF
A
REF
REF
CLK
≤ 1.5V
1
⁄
4
≤ 3.6V
≤ V
to
/2
/4
/4
/2
/2
/2
≤ 1.5V
≤ 80 MHz
3
D
⁄
4
of the minimum output range obtainable
V
V
V
V
CM
CM
CM
CM
REF
Input
Input
V
V
V
V
V
V
V
V
+ V
+ V
− V
− V
CM
CM
CM
CM
CM
CM
IN −
IN −
.
REF
REF
REF
REF
/2
/4
/4
/2
CM
, and be 180˚ out of
0000 0000 0000
0100 0000 0000
1000 0000 0000
0000 0000 0000
0100 0000 0000
1000 0000 0000
1100 0000 0000
1100 0000 0000
REF
1111 1111 1111
1111 1111 1111
, be centered
Output
Output
IN
+ and
20
1.2 Reference Pins
The ADC12L066 is designed to operate with a 1.0V refer-
ence, but performs well with reference voltages in the range
of 0.8V to 1.5V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC12L066. Increasing
the reference voltage (and the input signal swing) beyond
1.5V may degrade THD for a full-scale input, especially at
higher input frequencies. It is important that all grounds
associated with the reference voltage and the input signal
make connection to the analog ground plane at a single,
quiet point in that plane to minimize the effects of noise
currents in the ground path.
The ADC12L066 will perform well with reference voltages up
to 1.5V for full-scale input frequencies up to 10 MHz. How-
ever, more headroom is needed as the input frequency
increases, so the maximum reference voltage (and input
swing) will decrease for higher full-scale input frequencies.
The three Reference Bypass Pins (V
made available for bypass purposes only. These pins should
each be bypassed to ground with a 0.1 µF capacitor. Smaller
capacitor values will allow faster recovery from the power
down mode, but may result in degraded noise performance.
DO NOT LOAD these pins. Loading any of these pins may
result in performance degradation.
The nominal voltages for the reference bypass pins are as
follows:
The V
source (V
current is drawn from it. However, because the voltage at
this pin is half that of the V
a common mode source will result in reduced input head-
room (the difference between the V
peak signal voltage at either analog input) and the possibility
of reduced THD and SFDR performance. For this reason, it
is recommended that V
Volts. For high input frequencies it may be necessary to
increase this headroom to maintain THD and SFDR perfor-
mance. Alternatively, use V
1.3 Signal Inputs
The signal inputs are V
defined as
Figure 2 shows the expected input signal range.
Note that the nominal input common mode voltage is V
and the nominal input signals each run between the limits of
V
never exceed the voltage described as
to maintain dynamic performance.
The ADC12L066 performs best with a differential input with
each input centered around a common mode voltage, V
(minimum of 0.5V). The peak-to-peak voltage swing at both
V
reference voltage or the output data will be clipped.
The two input signals should be exactly 180˚ out of phase
from each other and of the same amplitude. For single
frequency (sine wave) inputs, angular errors result in a re-
duction of the effective full scale input. For a complex wave-
form, however, angular errors will result in distortion.
REF
IN
V
V
V
+ and V
RM
RP
RN
/2 and 3V
RM
= V
= V
= V
CM
RM
RM
pin may be used as a common mode voltage
A
IN
) for the analog input pins as long as no d.c.
/ 2
− should each not exceed the value of the
+ V
− V
Peak Input Voltage = V
REF
REF
REF
/2. The Peaks of the input signals should
V
IN
/ 2
/ 2
IN
A
= (V
+ and V
always exceed V
A
RN
IN +
supply pin, using these pins for
) – (V
for a V
IN
−. The input signal, V
A
IN
supply voltage and the
RP
CM
A
−)
, V
− 0.8
source.
RM
REF
and V
by at least 2
RN
) are
IN
REF
, is
CM