adc12l080civy National Semiconductor Corporation, adc12l080civy Datasheet - Page 19

• Manufacturer Part Number: adc12l080civy
• Description: 12-bit, 80 Msps, 450 Mhz Bandwidth A/d Converter With Internal Reference
• Manufacturer: National Semiconductor Corporation

Applications Information
3.3 PD
The PD pin, when high, holds the ADC12L080 in a power-
down mode to conserve power when the converter is not
being used. The power consumption in this state is 50 mW
and is not affected by the clock frequency, or by whether
there is a clock signal present. The output data pins are
undefined and the data in the pipeline is corrupted while in
the power down mode.
The Power Down Mode Exit Cycle time is determined by the
value of the capacitors on pins 30, 31 and 32. These capaci-
tors loose their charge in the Power Down mode and must
be recharged by on-chip circuitry before conversions can be
accurate. See Section 2.1
4.0 OUTPUTS
The ADC12L080 has 12 TTL/CMOS compatible Data Output
pins. The output data is present at these outputs while the
PD pin is low. While the t
output timing, a simple way to capture a valid output is to
latch the data on the rising edge of the conversion clock (pin
10).
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
FIGURE 4. Simple Application Circuit with Single-Ended to Differential Buffer
OD
time provides information about
(Continued)
19
conversion, the more instantaneous digital current flows
through V
spikes can cause on-chip noise and couple into the analog
circuitry, degrading dynamic performance. Adequate by-
passing, limiting output capacitance and careful attention to
the ground plane will reduce this problem. Additionally, bus
capacitance beyond the specified 15 pF/pin will cause t
increase, making it difficult to properly latch the ADC output
data. The result could be an apparent reduction in dynamic
performance.
To minimize noise due to output switching, minimize the load
currents at the digital outputs. This can be done by connect-
ing buffers between the ADC outputs and any other circuitry
(74ACQ541, for example). Only one driven input should be
connected to each output pin. Additionally, inserting series
100Ω resistors at the digital outputs, close to the ADC pins,
will isolate the outputs from trace and other circuit capaci-
tances and limit the output currents, which could otherwise
result in performance degradation. See Figure 4.
While the ADC12L080 will operate with V
to 1.8V, t
external timing when using reduced V
OD
DR
and DR GND. These large charging current
increases with reduced V
DR
.
DR
DR
. Be careful of
voltages down
www.national.com
OD
20061013
to