adc12eu050eb National Semiconductor Corporation, adc12eu050eb Datasheet - Page 13

• Manufacturer Part Number: adc12eu050eb
• Description: Adc12eu050 Ultra-low Power, Octal, 12-bit, 40-50 Msps Sigma-delta Analog-to-digital Converter
• Manufacturer: National Semiconductor Corporation

Serial Interface
t
t
t
t
t
t
t
t
t
t
t
t
Symb
SSELS
SSELH
WS
WH
SCLK
SCLKL
SCLKH
SCLKR
SCLKF
SSELHI
RS
RH
AC and Timing Characteristics (Serial Interface)
Unless otherwise specified, the following conditions apply: V
= 5pF; 100Ω terminated at the receiver; f
apply for T
Note 1: Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
Note 2: Operating Ratings indicate conditions for which the device is guaranteed to be functional, but do not guarantee specific performance limits. Guaranteed
specifications and test conditions are specified in the Electrical Characterisitcs section. Operation of the device beyond the Operating Ratings is not recommended
as it may degrade the device lifetime.
Note 3: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 4: Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not
guaranteed.
Note 5: This parameter is specified in dBFS. This indicates the value which would be obtained with a full-scale input.
Note 6: As the filter is a digital circuit, Digital Decimation Filter Characteristics scale with input clock frequency, f
Note 7: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 8: The combination of common mode and voltage swing on the clock input must ensure that the positive voltage peaks are not above VDR and the negative
votlage peaks are not below AGND.
Note 9: See the "Clock Conditioner Owner's Manual", Chapter 2 (www.national.com/appinfo/interface/files/clk_conditioner_owners_manual.pdf) for a discussion
on jitter.
ol
S
S
S
S
S
S
S
S
S
S
S
transaction
S
SEL
SEL
DATA
DATA
CLK
CLK
CLK
CLK
CLK
SEL
DATA
DATA
A
setup time
hold time
high time
period
low time
high time
rise time
fall time
= +25°C.
valid hold time, read transaction
setup time, write transaction
hold time, write transaction
valid setup time, read
Parameter
CLK
= 50MHz; f
Applies to read and write transactions
S
= 50MSPS. Boldface limits apply for T
A
Conditions
= V
13
D
= 1.2V; V
DR
= 1.2V; V
REF
CLK
(Note
Typical
= internal; R
.
250
250
250
250
450
450
500
100
250
50
50
1
A
4)
= T
MIN
Limits
0.2
15
10
10
REF
-5
to T
= 10kohm ±1%; C
MAX
; All other limits
www.national.com
ns (max)
ns (max)
µs (min)
ns (min)
ns (min)
ns (min)
ns (min)
Units
ns
ns
ns
ns
ns
L