adc10080cimt National Semiconductor Corporation, adc10080cimt Datasheet - Page 16

• Manufacturer Part Number: adc10080cimt
• Description: 10-bit, 80 Msps, 3v, 78.6 Mw A/d Converter
• Manufacturer: National Semiconductor Corporation

www.national.com
Functional Description
The ADC10080 uses a pipeline architecture and has error
correction circuitry to help ensure maximum performance.
Differential analog input signals are digitized to 10 bits. In
differential mode each analog input signal should have a
peak-to-peak voltage equal to 1.0V, 0.75V or 0.5V, depend-
ing on the state of the IRS pin (pin 5), and be centered
around V
single ended operation is desired, V
V
applied to V
range of V
1.0V peak-to-peak, depending on the state or the IRS pin
(pin 5).
Applications Information
1.0 ANALOG INPUTS
The ADC10080 has two analog signal inputs, V
These two pins form a differential input pair. There is one
common mode pin V
mon mode input voltage.
1.1 REFERENCE PINS
The ADC10080 is designed to operate with a 1.2V reference.
The voltages at V
the reference voltage. It is very important that all grounds
associated with the reference voltage and the input signal
make connection to the analog ground plane at a single point
to minimize the effects of noise currents in the ground path.
The three Reference Bypass Pins V
are made available for bypass purposes only. These pins
should each be bypassed to ground with a 0.1 µF capacitor.
DO NOT LOAD these pins.
1.2 V
This pin supplies a voltage for possible use to set the com-
mon mode input voltage. This pin may also be connected to
V
pin should be byassed with at least a 0.1 uF capacitor.
1.3 SIGNAL INPUTS
The signal inputs are V
tude is defined as V
cally in Figure 3:
A single ended input signal is shown in Figure 4.
COM
IN
-, so that V
FIGURE 3. Input Voltage Waveforms for a 2V
COM
pin (pin 4). A single ended input signal may then be
CM
PIN
CM
IN
and be 180˚ out of phase with each other. If
. The signal amplitude should be 2.0V, 1.5V or
IN
+, and should have an average value in the
+ may be used as a single ended input. This
COM
IN
Differential Input
COM
+ − V
, V
IN
+ and V
REFT
that may be used to set the com-
IN
− and is represented schemati-
, and V
IN
−. The input signal ampli-
REF
IN
REFB
- may be tied to the
, V
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are derived from
REFT
IN
+ and V
and V
P-P
REFB
IN
−.
,
16
The internal switching action at the analog inputs causes
energy to be output from the input pins. As the driving source
tries to compensate for this, it adds noise to the signal. To
prevent this, use 18Ω series resistors at each of the signal
inputs with a 25 pF capacitor across the inputs, as can be
seen in Figure 5. These components should be placed close
to the ADC because the input pins of the ADC is the most
sensitive part of the system and this is the last opportunity to
filter the input. The two 18Ω resistors and the 25 pF capaci-
tor form a low-pass filter with a -3 dB frequency of 177 MHz
.
1.4 CLK PIN
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 20 MHz to 80 MHz with rise and fall times of less
than 2 ns. The trace carrying the clock signal should be as
short as possible and should not cross any other signal line,
analog or digital, not even at 90˚. The CLK signal also drives
an internal state machine. If the CLK is interrupted, or its
frequency is too low, the charge on internal capacitors can
dissipate to the point where the accuracy of the output data
will degrade. This is what limits the lowest sample rate to
20 MSPS. The duty cycle of the clock signal can affect the
performance of any A/D Converter. Because achieving a
precise duty cycle is difficult, the ADC10080 is designed to
maintain performance over a range of duty cycles. While it is
specified and performance is guaranteed with a 50% clock
duty cycle, performance is typically maintained over a clock
duty cycle range of 40% to 60%.
1.5 STBY PIN
The STBY pin, when high, holds the ADC10080 in a power-
down mode to conserve power when the converter is not
being used. The power consumption in this state is 15 mW.
The output data pins are undefined in this mode. Power
consumption during power-down is not affected by the clock
frequency, or by whether there is a clock signal present. The
data in the pipeline is corrupted while in the power down.
1.6 DF PIN
The DF pin, when high, forces the ADC10080 to output the
2’s complement data format. When DF is tied low, the output
format is offset binary.
1.7 IRS PIN
The IRS (Input Range Select) pin defines the input signal
amplitude that will produce a full scale output. The table
below describes the function of the IRS pin.
FIGURE 4. Input Voltage Waveform for a 2V
Ended Input
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P-P
Single