kad5514p Kenet Inc., kad5514p Datasheet - Page 22

• Manufacturer Part Number: kad5514p
• Description: 14-bit, 250/210/170/125msps Adc
• Manufacturer: Kenet Inc.

and LSB-first modes, respectively. In MSB-first mode
the address is incremented for multi-byte transfers,
while in LSB-first mode it’s decremented.
In the default mode the MSB is R/W, which deter-
mines if the data is to be read (active high) or writ-
ten. The next two bits, W1 and W0, determine the
number of data bytes to be read or written (see Ta-
ble 6). The lower 13 bits contain the first address for
the data transfer. This relationship is illustrated in Fig-
ure 37, and timing values are given in the Switching
Specifications section.
After the instruction/address bytes have been read,
the appropriate number of data bytes are written to
or read from the ADC (based on the R/W bit status).
The data transfer will continue as long as CSB remains
low and SCLK is active. Stalling of the CSB pin is al-
lowed at any byte boundary (instruction/address or
data) if the number of bytes being transferred is three
or less. For transfers of four bytes or more, CSB is al-
lowed stall in the middle of the instruction/address
bytes or before the first data byte. If CSB transitions to
a high state after that point the state machine will
reset and terminate the data transfer.
Figures 38 and 39 illustrate the timing relationships for
2-byte and N-byte transfers, respectively. The opera-
tion for a 3-byte transfer can be inferred from these
diagrams.
SPI Configuration
Address 0x00: chip_port_config
Bit ordering and SPI reset are controlled by this regis-
ter. Bit order can be selected as MSB to LSB (MSB first)
or LSB to MSB (LSB first) to accommodate various mi-
crocontrollers.
Bit 7
Bit 6
Bit 5
KAD5514P
SDO Active
LSB First
Setting this bit high configures the SPI to inter-
pret serial data as arriving in LSB to MSB order.
Soft Reset
Table 6. Byte Transfer Selection
[W1:W0]
00
01
10
11
Bytes Transferred
4 or more
1
2
3
Preliminary
Bit 4
Bits 3:0 These bits should always mirror bits 4:7 to
Address 0x02: burst_end
If a series of sequential registers are to be set, burst
mode can improve throughput by eliminating redun-
dant addressing. In 3-wire SPI mode the burst is
ended by pulling the CSB pin high. If the device is
operated in 2-wire mode the CSB pin is not available.
In that case, setting the burst_end address deter-
mines the end of the transfer. During a write opera-
tion, the user must be cautious to transmit the correct
number of bytes based on the starting and ending
addresses.
Bits 7:0 Burst End Address
Device Information
Address 0x08: chip_id
Address 0x09: chip_version
The generic die identifier and a revision number, re-
spectively, can be read from these two registers.
Indexed Device Configuration/
Control
Address 0x10: device_index_A
A common SPI map, which can accommodate sin-
gle-channel or multi-channel devices, is used for all
Kenet ADC products. Certain configuration com-
mands (identified as Indexed in the SPI map) can be
executed on a per-converter basis. This register de-
termines which converter is being addressed for an
Indexed command. It is important to note that only a
single converter can be addressed at a time.
This register defaults to 00h, indicating that no ADC is
addressed. Error code ‘AD’ is returned if any indexed
register is read from without properly setting de-
vice_index_A.
Address 0x20: offset_coarse
Address 0x21: offset_fine
The input offset of each ADC core can be adjusted
in fine and coarse steps. Both adjustments are made
via an 8-bit word as detailed in Table 7.
Setting this bit high resets all SPI registers to
default values.
Reserved
This bit should always be set high.
avoid ambiguity in bit ordering.
This register value determines the ending ad-
dress of the burst data.
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