kad5612p Kenet Inc., kad5612p Datasheet - Page 23

• Manufacturer Part Number: kad5612p
• Description: Dual 12-bit, 250/210/170/125msps A/d Converter
• Manufacturer: Kenet Inc.

Internal clock signals are generated by a delay-
locked loop (DLL), which has a finite operating
range. Table 15 shows the allowable sample rate
ranges for the slow and fast settings.
The output_mode_B and config_status registers are
used in conjunction to select the frequency range of
the DLL clock generator. The method of setting these
options is different from the other registers.
The procedure for setting output_mode_B is shown in
Figure 41. Read the contents of output_mode_B and
config_status and XOR them. Then XOR this result with
the desired value for output_mode_B and write that
XOR result to the register.
Device Test
The KAD5612 can produce preset or user defined
patterns on the digital outputs to facilitate in-situ test-
ing. A static word can be placed on the output bus,
or two different words can alternate. In the alternate
mode, the values defined as Word 1 and Word 2 (as
shown in Table 16) are set on the output bus on alter-
nating clock phases. The test mode is enabled asyn-
chronously to the sample clock, therefore several
sample clock cycles may elapse before the data is
present on the output bus.
Address 0xC0: test_io
Bits 7:6 User Test Mode
The four LSBs in this register (Output Test Mode) deter-
mine the test pattern in combination with registers
0xC2 through 0xC5. Refer to Table 17.
KAD5612P
DLL Range
Figure 41 Setting output_mode_B register
These bits set the test mode to static (0x00) or
alternate (0x01) mode. Other values are re-
served.
Slow
Fast
Table 15. DLL Ranges
MIN
40
80
f
MAX
S
100
MAX
MSPS
MSPS
Unit
Address 0xC2: user_patt1_lsb
Address 0xC3: user_patt1_msb
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
Address 0xC2: user_patt2_lsb
Address 0xC3: user_patt2_msb
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
Output Test Mode
Negative Full-Scale
Positive Full-Scale
Table 16. Output Test Modes
Checkerboard
User Pattern
0xC0[3:0]
One/Zero
Reserved
Reserved
Midscale
Off
user_patt1
0xAAAA
Word 1
0x8000
0x0000
0xFFFF
0xFFFF
N/A
N/A
user_patt2
Word 2
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0x5555
0x0000
N/A
N/A
N/A
N/A
N/A