kad5610p Kenet Inc., kad5610p Datasheet - Page 15

• Manufacturer Part Number: kad5610p
• Description: Dual 10-bit, 250/210/170/125msps A/d Converter
• Manufacturer: Kenet Inc.

The calibration sequence is initiated on the rising
edge of RESETN, as shown in Figure 28. The over-
range output (OR) is set high once RESETN is pulled
low, and remains in that state until calibration is com-
plete. The OR output returns to normal operation at
that time, so it’s important that the analog input be
within the converter’s full-scale range in order to ob-
serve the transition. If the input is in an over-range
condition the OR pin will stay high and it will not be
possible to detect the end of the calibration cycle.
W h i l e R E S E T N i s l o w , t h e o u t p u t c l o c k
(CLKOUTP/CLKOUTN) stops toggling and is set low.
Normal operation of the output clock resumes at the
next input clock edge (CLKP/CLKN) after RESETN is
deasserted. At 250MSPS the nominal calibration time
is 300ms.
User-Initiated Reset
Recalibration of the ADC can be initiated at any
time by driving the RESETN pin low for a minimum of
one clock cycle. An open-drain driver with a drive
strength of less than 0.5mA is recommended. As is the
case during power-on reset, the SDO, RESETN and
DNC pins must be in the proper state for the calibra-
tion to successfully execute.
Analog Input
Each ADC core contains a fully differential input
(AINP/AINN, BINP/BINN) to the sample and hold am-
plifier (SHA). The ideal full-scale input voltage is 1.45V,
centered at the VCM voltage of 0.535V as shown in
Figure 29.
Best performance is obtained when the analog in-
puts are driven differentially. The common mode out-
put voltage, VCM, should be used to properly bias
the inputs as shown in Figures 30 through 32.
Rev 0.5.1 Preliminary
KAD5610P
Figure 28. Calibration Timing
An RF transformer will give the best noise and distor-
tion performance for wideband and/or high interme-
diate frequency (IF) inputs. Two different transformer
input schemes are shown in Figures 30 and 31.
A back-to-back transformer scheme is used to im-
prove common mode rejection, which keeps the
common mode level of the input matched to VCM.
The value of the shunt resistor should be determined
based on the desired load impedance. The differen-
tial input resistance of the KAD5610P is 1000Ω.
The SHA design uses a switched capacitor input
stage, which creates charge kick-back when the
sampling capacitance is reconnected to the input
voltage. This kick-back creates a disturbance at the
input which must settle before the next sampling
point. Lower source impedance will result in faster
settling and improved performance. Therefore a 1:1
transformer and low shunt resistance are recom-
mended for optimal performance.
Figure 31. Transmission-line Transformer Input for High
Figure 30. Transformer Input for General Purpose
Figure 29. Analog Input Range
IF Applications
Applications
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