clc5623 National Semiconductor Corporation, clc5623 Datasheet - Page 9

• Manufacturer Part Number: clc5623
• Description: Triple, High Output, Video Amplifier
• Manufacturer: National Semiconductor Corporation

Inverting gain applications:
The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.
Use C
greater frequency range. C
of the amplifier’s output impedance with frequency.
Power Dissipation
Follow these steps to determine the power consumption
of the CLC5623:
The maximum power that the DIP and SOIC packages
can dissipate at a given temperature is illustrated in
Figure 11. The power derating curve for any CLC5623
package can be derived by utilizing the following
equation:
where
T
V
V
JA
amb
1
2
+
+
-
-
= Thermal resistance, from junction to ambient,
= Ambient temperature (°C)
for a given package (°C/W
R
R
6
Connect R
Make the resistors R
Make R
1
4
Figure 10: Transmission Line Matching
1. Calculate the quiescent (no-load) power:
2. Calculate the RMS power at the output stage:
3. Calculate the total RMS power:
to match the output transmission line over a
Figure 11: Power Derating Curves
P
P
are the RMS voltage and current across the
external load.
P
1.0
0.8
0.6
0.4
0.2
0
amp
o
t
-40 -20
= P
= (V
Z
Z
0
0
5
= I
II R
amp
3
CC
CC
0
Ambient Temperature ( C)
directly to ground.
g
+ P
- V
20 40 60 80 100 120
R
R
= Z
(V
(175
2
5
R
R
3
g
load
CC
o
o
6
.
) (I
compensates for the increase
- V
CLC5623
4
+
-
IM
JA
, R
1/3
T
R
load
EE
IN
amb
f
6
, and R
)
), where V
)
C
140 160
R
6
6
7
equal to Z
180
load
Z
0
and I
o
R
.
load
7
V
o
9
Layout Considerations
A proper printed circuit layout is essential for achieving
high
evaluation boards for the CLC5623 (CLC730075-DIP,
CLC730074-SOIC) and suggests their use as a guide for
high frequency layout and as an aid for device testing and
characterization.
General layout and supply bypassing play major roles in
high frequency performance. Follow the steps below as
a basis for high frequency layout:
Evaluation Board Information
A data sheet is available for the CLC730075/ CLC730074
evaluation boards.
provides:
The evaluation boards are designed to accommodate
dual supplies. The boards can be modified to provide
single supply operation. For best performance; 1) do
not connect the unused supply, 2) ground the unused
supply pin.
SPICE Models
SPICE models provide a means to evaluate amplifier
designs. Free SPICE models are available for National’s
monolithic amplifiers that:
The readme file that accompanies the diskette lists
released models, and provides a list of modeled parame-
ters. The application note OA-18, Simulation SPICE
Models for National’s Op Amps, contains schematics and
a reproduction of the readme file.
frequency
Include 6.8 F tantalum and 0.1 F ceramic
capacitors on both supplies.
Place the 6.8 F capacitors within 0.75 inches
of the power pins.
Place the 0.1 F capacitors less than 0.1 inches
from the power pins.
Remove the ground plane under and around the
part, especially near the input and output pins to
reduce parasitic capacitance.
Minimize all trace lengths to reduce series
inductances.
Use flush-mount printed circuit board pins for
prototyping, never use high profile DIP sockets.
Evaluation board schematics
Evaluation board layouts
General information about the boards
Support Berkeley SPICE 2G and its many derivatives
Reproduce typical DC, AC, Transient, and Noise
performance
Support room temperature simulations
performance.
The evaluation board data sheet
National
http://www.national.com
provides