clc5612 National Semiconductor Corporation, clc5612 Datasheet - Page 14

• Manufacturer Part Number: clc5612
• Description: Dual, High Output, Programmable Gain Buffer
• Manufacturer: National Semiconductor Corporation

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Application Division
Load Termination
The CLC5612 can source and sink near equal amounts of
current. For optimum performance, the load should be tied to
V
Driving Cables and Capacitive Loads
When driving cables, double termination is used to prevent
reflections. For capacitive load applications, a small series
resistor at the output of the CLC5612 will improve stability
and settling performance. The Frequency Response vs. C
plot, shown below in Figure 10 , gives the recommended
series resistance value for optimum flatness at various
capacitive loads.
Transmission Line Matching
One method for matching the characteristic impedance (Z
of a transmission line or cable is to place the appropriate
resistor at the input or output of the amplifier. Figure 11
shows typical inverting and non-inverting circuit configura-
tions for matching transmission lines.
Non-inverting gain applications:
• Connect pin 2 as indicated in the table in the Closed Loop
cm
V
FIGURE 9. Dual Supply, A
Gain Selection section.
in
.
1M
FIGURE 10. Frequency Response vs. C
R
V
1k
t
V
o
V
+
-
o
EE
= 1V
C
R
1k
L
s
0.1 F
6.8 F
pp
= 100pF
= 17.4
2
3
1
4
+
R
C
s
C
R
Frequency (Hz)
L
s
C
1k
= 49.9
R
L
CLC5612
= 10pF
L
= 1000pF
s
1k
= 6.7
10M
+
1k
-
+
-
V
1k
1k
= +2V/V Configuration
Note: Channel 2 not shown.
(Continued)
8
7
6
5
V
CC
100M
6.8 F
0.1 F
DS015001-48
+
DS015001-47
L
o
L
)
14
• Make R
• Use R
Inverting gain applications:
• Connect R
• Make the resistors R
• Make R
The input and output matching resistors attenuate the signal
by a factor of 2, therefore additional gain is needed. Use C
to match the output transmission line over a greater
frequency range. C
amplifier’s output impedance with frequency.
Power Dissipation
Follow these steps to determine the power consumption of
the CLC5612:
1. Calculate the quiescent (no-load) power: P
(V
2. Calculate the RMS power at the output stage: P
CC
and current across the external load.
3. Calculate the total RMS power: P
The maximum power that the DIP and SOIC, packages can
dissipate at a given temperature is illustrated in Figure 12 .
The power derating curve for any CLC5612 package can be
derived by utilizing the following equation:
where T
given package (˚C/W)
V
V
JA
1
2
CC
-V
caused by the transmission line, or by parasitics
=Thermal resistance, from junction to ambient, for a
+
+
-
-
−V
load
R
R
EE
4
1
FIGURE 11. Transmission Line Matching
)(I
amb
)
3
load
1
5
FIGURE 12. Power Derating Curve
, R
\R
= Ambient temperature (˚C)
to isolate the amplifier from reactive loading
Z
Z
), where V
3
g
0
0
2
=Z
directly to ground.
,R
0
6
.
6
R
R
and R
5
R
2
compensates for the increase of the
3
4
load
, R
7
2
3
1
4
equal to Z
6
and I
, and R
1k
CLC5612
1k
1k
-
+
+
-
load
1k
t
7
= P
0
equal to Z
are the RMS voltage
8
7
6
5
.
amp
Note: Channel 2 not shown.
DS015001-51
C
R
6
6
+P
o
0
amp
.
Z
0
0
DS015001-49
= I
= (V
CC
R
6
7
V
o