lm8333ggr8x National Semiconductor Corporation, lm8333ggr8x Datasheet - Page 11

• Manufacturer Part Number: lm8333ggr8x
• Description: Mobile I/o Companion Supporting Key-scan, I/o Expansion, Pwm, And Access.bus Host Interface
• Manufacturer: National Semiconductor Corporation

9.6 WAKE-UP FROM HALT MODE
Any bus transaction initiated by the host may encounter the
LM8333 device in Halt mode or busy with processing data,
such as controlling the FIFO buffer or executing interrupt ser-
vice routines.
Figure 10 shows the case in which the host sends a command
while the LM8333 is in Halt mode (CPU clock is stopped). Any
activity on the ACCESS.bus wakes up the LM8333, but it
cannot acknowledge the first bus cycle immediately after
wake-up.
The host drives a Start condition followed by seven address
bits and a R/W bit. The host then releases SDA for one clock
period, so that it can be driven by the LM8333.
If the LM8333 does not drive SDA low during the high phase
of the clock period immediately after the R/W bit, the bus cycle
10.0 Interrupts
10.1 INTERRUPT CODE
The interrupt code is read and acknowledged with the
READ_INT command (0xD0). This command clears the code
and deasserts the IRQ output. Table 6 shows the format of
the interrupt code.
10.2 ERROR CODE
If the LM8333 reports an error, the READ_ERROR command
(0xF0) is used to read and clear the error code. Table 7 shows
the format of the error code.
Bit
ERROR
EX_1
EX_0
KEYPAD
7
0
7
0
FIFOOVR
6
0
6
Description
An error condition occurred.
A rising or falling edge was detected on GEN_IO_1.
A rising or falling edge was detected on GEN_IO_0.
A key-press or key-release event occurred.
FIGURE 10. LM8333 Responds with NACK, Host Retries Command
5
0
5
0
4
0
TABLE 6. Interrupt Code
NOINT
TABLE 7. Error Code
4
11
ERROR
3
terminates without being acknowledged (shown as NACK in
Figure 10). The host then aborts the transaction by sending
a Stop condition. After aborting the bus cycle, the host may
then retry the bus cycle. On the second attempt, the LM8333
will be able to acknowledge the slave address, because it will
be in Active mode.
Alternatively, the I
byte (00000001), which will not be acknowledged by any de-
vice. This byte can be used to wake up the LM8333 from Halt
mode.
The LM8333 may also stall the bus transaction by pulling the
SCL low, which is a valid behavior defined by the I
fication.
Note that when only one of the interrupt-capable pins
GEN_IO_0 or GEN_IO_1 is configured as an interrupt input,
bits 1 and 2 are both set when an interrupt occurs. When both
GEN_IO_0 and GEN_IO_1 pins are configured as interrupt
inputs, only one bit corresponding to the interrupt source is
set when an interrupt occurs.
3
0
EX_1
KEYOVR
2
2
C specification allows sending a START
2
EX_0
CMDUNK
1
1
20210612
www.national.com
KEYPAD
CMDOVR
2
C speci-
0
0