dac1054 National Semiconductor Corporation, dac1054 Datasheet - Page 10

• Manufacturer Part Number: dac1054
• Description: Quad 10-bit Voltage-output Serial D/a Converter With Readback
• Manufacturer: National Semiconductor Corporation

Digital Interface
The DAC1054 has two interface modes a WRITE mode
and a READ mode The WRITE mode is used to convert a
10-bit digital input word into a voltage The READ mode is
used to read back the digital data that was sent to one or all
of the DACs The WRITE mode maximum clock rate is
10 MHz READ mode is limited to a 5 MHz maximum clock
rate These modes are selected by the appropriate setting
of the RD WR bit which is part of the instruction byte The
instruction byte precedes the data byte at the DI pin In both
modes a high level on the Start Bit (SB) alerts the DAC to
respond to the remainder of the input stream
Table I lists the instruction set for the WRITE mode when
writing to only a single DAC and Table II lists the instruction
set for a global write Bits A0 and A1 select the DAC to be
written to The DACs are always written to MSB first All
DACs will be written to sequentially if the global bit (G) is
Bit
Bit
SB
1
1
1
1
1
1
1
1
SB
1
1
1
1
RD WR
Bit
0
0
0
0
0
0
0
0
RD WR
Bit
2
TABLE I WRITE Mode Instruction Set (Writing to a Single DAC)
0
0
TABLE II WRITE Mode Instruction Set (Writing to all DACs)
Bit
2
G
0
0
0
0
0
0
0
0
3 Bit
Bit
G
1
1
U
0
0
0
0
1
1
1
1
3
4 Bit
Bit
A1
U
0
1
0
0
1
1
0
0
1
1
4
5 Bit
Write all DACs no update of outputs
Write all DACs update all outputs on CS rising edge
A0
0
1
0
1
0
1
0
1
10
6
high DAC 1 is written to first then DACs 2 3 and 4 (in that
order) For a global write bits A0 and A1 of the instruction
byte are not required (see Figure 2 timing diagram) If the
update bit (U) is high then the DAC output(s) will be updat-
ed on the rising edge of CS otherwise the new data byte
will be placed only in the input register Chip Select (CS)
must remain low for at least one clock cycle after the last
data bit has been entered (See Figures 1 and 2 )
When the U bit is set low an asynchronous update of all the
DAC outputs can be achieved by taking AU low The con-
tents of the input registers are loaded into the DAC regis-
ters with the update occurring on the falling edge of AU CS
must be held high during an asynchronous update
All DAC registers will have their contents reset to all zeros
on power up
Write DAC 1 no update of DAC outputs
Write DAC 2 no update of DAC outputs
Write DAC 3 no update of DAC outputs
Write DAC 4 no update of DAC outputs
Write DAC 1 update DAC 1 on CS rising edge
Write DAC 2 update DAC 2 on CS rising edge
Write DAC 3 update DAC 3 on CS rising edge
Write DAC 4 update DAC 4 on CS rising edge
Description
Description