atf1508re ATMEL Corporation, atf1508re Datasheet
atf1508re
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atf1508re Summary of contents
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... Advanced Digital CMOS Technology – 100% Tested – Completely Reprogrammable – 10,000 Program/Erase Cycles – 20-year Data Retention – 2000V ESD Protection – 200 mA Latch-up Immunity • Security Fuse Feature • Hot-Socketing Supported High- performance CPLD ATF1508RE 3682A–PLD–10/08 ...
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... PLDs. The ATF1508RE’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications. The ATF1508RE has bi-directional I/O pins, four dedicated input pins, 1 internal voltage regulator supply input pin (VCCIRI), 6 I/O VCC pins (VCCIOA and VCCIOB), 8 ground pins (GND and 1 internal voltage regulator output pin (VCCIR0) ...
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... VCCIOA 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 Note: VCCIRO (P39 for 100 TQFP) needs to be left floating and used for coupling (use 2.2 µF/or 4.7 µF X7R chip CAP and 470 pF NPO chip CAP. 3682A–PLD–10/08 ATF1508RE 75 I/O 74 GND 73 I/O/TDO 72 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 VCCIOB ...
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... I/O P VCCIRO I/O I/O Notes: 1. The 132-ball CBGA package 1 size with 0.5 mm ball spacing. 2. VCCIRO (P1 for 132 CBGA) needs to be left floating and connect to coupling CAP (use 2.2 µF/or 4.7 µF X7R chip CAP and 470PF NPO chip CAP. ATF1508RE I/O I/O NC ...
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... Figure 1-3. Block Diagram 10 3682A–PLD–10/ ATF1508RE 5 ...
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... OR/XOR/CASCADE logic, a flip-flop, output select and enable, and logic array inputs. A security fuse, when programmed, protects the contents of the ATF1508RE. Two bytes (16 bits) of User Electronic Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Electronic Signature is accessible regard- less of the state of the security fuse ...
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... OR/XOR/CASCADE Logic The ATF1508RE’s logic structure is designed to efficiently support all types of logic. Within a sin- gle macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with minimal additional delay. The macrocell’ ...
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... Programmable Pin-keeper Option for Inputs and I/Os The ATF1508RE offers the option of individually programming each of its input or I/O pin so that pin-keeper circuit can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents undriven input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power con- sumption and system noise ...
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... I/O Bank The I/O pins of the ATF1508RE are grouped into two banks, Bank A and Bank B. Bank A com- prises of I/O pins for macrocells (Logic Block and D), and it is powered Bank B comprises of I/O pins for macrocells 65 to 128 (Logic Block and H), and ...
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... ATF1508RE to operate properly (see The ATF1508RE CPLD also supports MultiVolt I/O interface feature, which allows seamless interface to other devices at 1.5V, 1.8V, 2.5V, or 3.3V logic levels. The ATF1508RE device has two I/O banks, each bank can be supplied with an independent VCCIO (VCCIOA or VCCIOB). Figure 2-3. ...
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... PLD for functional mode. When the device is in the ISC programming mode, all user I/Os are held in the high impedance state. The ISC mode is best suited for working with the ATF1508RE device in a design development or production environment. Configuration of the ATF1508RE device done via a Download Cable ...
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... ISP Programming Protection The ATF1508RE has a special feature that locks the device and prevents the inputs and I/O from driving if the programming process is interrupted for any reason. The I/O pins default to high-Z state during such a condition. All ATF1508RE devices are initially shipped in the erased state, thereby making them ready to use for ISP ...
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... JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells is shown below. Figure 6-1. Note: 3682A–PLD–10/08 BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins) The ATF1508RE has a pull-up option on TMS and TDI pins. This feature is selected as a design option. ATF1508RE 13 ...
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... Figure 6-2. 7. Design Software Support ATF1508RE designs are supported by several third-party tools. Automated fitters allow logic synthesis using a variety of high-level description languages such as VHDL party synthesis and simulation tools from Mentor Graphics tools. 8. Electrical Specifications Table 8-1. Absolute Maximum Ratings* Operating Temperature...................................–40° +85° C Storage Temperature ....................................– ...
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... I/O Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. 3682A–PLD–10/08 Commercial Max Units ATF1508RE Industrial 0° 70° C -40° 85° C Conditions 1.0 MHz 0V 1.0 MHz OUT 15 ...
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... LVCMOS 3.3V & LVTTL (HD: High Drive, LD: Low Drive) V Input Low-voltage IL V Input High-voltage IH V Output Low-voltage OL V Output High-voltage OH LVCMOS 2.5V V Input Low-voltage IL V Input High-voltage IH V Output Low-voltage OL V Output High-voltage OH ATF1508RE 16 Condition V = 3.3V 3.3V CCIO CCIRI (1) Core V = 3.3V 3.3V CCIRI CCIO V = 3.3V 3.3V, CCIRI CCIO MHz V = 3.3V 3.3V, CCIRI CCIO ...
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... CCIO V THL Min Max 0.68 0.73 0.81 0.88 Conditions mA 2.3V OH CCIO mA 2.3V OL CCIO may not exceed ± should track the variations in V REF REF REF of receiving devices. REF ATF1508RE Min Typ Max -0.3 0. CCIO 1.2 3.9 0.45 0 0.45V CCIO V - 0.45V CCIO -0.3 0. CCIO 1.2 3.9 0.45 0 0.45V CCIO ...
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... Peak-to-peak noise on V REF transmitting device must track Timing Model Input Delay t IN (+t ) SCH Switch Matrix t UIM ATF1508RE 18 Conditions mA CCIO mA 2.3V OL CCIO may not exceed ± should track the variations in V REF REF of receiving devices ...
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... Note: 3682A–PLD–10/08 V CCIO R 1 Device Under Test 350 Ohm 300 Ohm 200 Ohm 150 Ohm C includes test fixtures and probe capacitance. L ATF1508RE Test Point 350 Ohm 35 pF 300 Ohm 35 pF 200 Ohm 35 pF 150 Ohm ...
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... Fast Input Delay FIN t Foldback Term Delay SEXP t Cascade Logic Delay PEXP t Logic Array Delay LAD t Logic Control Delay LAC t Internal Output Enable Delay IOE Output Buffer Delay (HD) t OD1 (High Drive pF) L ATF1508RE 20 -5 Min Max 5.0 7 4.2 2 0.5 6 1.25 1.25 1.7 0.50 6.5 1.75 1.75 3 333 4 ...
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... SSTL is not supported for low drive output (LD). 3682A–PLD–10/08 ( 1.5V CCIO V = 1.8V CCIO = 35 pF 2.5V CCIO V = 3.3V CCIO V = 1.5V CCIO V = 1.8V CCIO V = 2.5V CCIO V = 3.3V CCIO = 5 pF 1.5V CCIO V = 1.8V Level CCIO CCIO V = 2.5V CCIO V = 3.3V CCIO V = 2.5V CCIO V = 3.3V CCIO V = 2.5V CCIO V = 3.3V CCIO ATF1508RE -5 -7 Min Max Min Max 5.0 6.0 4.5 5.5 3.5 4.5 3.0 4.0 6.0 7.0 5.5 6.5 4.5 5.5 4.0 5 1.7 2.2 0.5 0.6 0.5 0.6 0.5 0.6 0.7 1.2 1.2 1.2 1.8 1.8 2.5 3 1.8 2 1.75 2 1.75 2 0.5 0.8 1.5 2 6.5 8.5 5.5 7.5 5.25 7 ...
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... Power-down Mode The ATF1508RE includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply cur- rent is reduced to less than 100 µA. During power-down, all output data and internal logic states are latched and held ...
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... ATF1508RE Dedicated Pinouts Table 13-1. Dedicated Pin INPUT / OE2 / GCLK2 INPUT / GCLR INPUT / OE1 INPUT / GCLK1 I/O / GCLK3 I (1, I/O / TDI (JTAG) I/O / TMS (JTAG) I/O / TCK (JTAG) I/O / TDO (JTAG) GND V CCIRI V CCIRO V CCIOA V CCIOB N Signal Pins # User I/O Pins OE (1, 2) GCLR GCLK ( (1, 2) TDI, TMS, TCK, TDO ...
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... Table 13-2. ATF1508RE I/O Pinouts Logic MC Block PD1 B/VREFA TDI ATF1508RE 24 100-lead ...
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... Table 13-2. ATF1508RE I/O Pinouts (Continued) Logic MC Block PD2 F/VREFB TCK 3682A–PLD–10/08 ...
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... VCCIRI = 3.3V Over Frequency, Room Temp 800 600 400 200 0 0 0.025 0.1 0.2 0.5 Frequency (MHz) OUTPUT SINK CURRENT(IOL) VS. OUTPUT VOLTAGE (VCCIRI = 3.3V, VCCIO = 1.5-3.3V 25C), High Drive 160 120 OUTPUT VOLTAGE ( V ) ATF1508RE Freq. (MHz) 25 Iccio_Vccio_1.5V 20 Iccio_Vccio_1.8V Iccio_Vccio_2.5V 15 Iccio_Vccio_3.3V 10 Iccint_Vccio_3. Iccio_Vccio_1.5V 25 Iccio_Vccio_1 ...
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... I/O PIN VOLTAGE ( V ) 3682A–PLD–10/08 OUTPUT SOURCE CURRENT(IOH) VS. OUTPUT VOLTAGE (VCCIRI = 1.8V, VCCIO =1.5-3.3V 25C), Low Drive 0 -5 1.5V -10 1.8V 2.5V -15 3.3V -20 -25 OUTPUT VOLTAGE ( V ) INPUT & I/O CURRENT VS. INPUT VOLTAGE VCCIRI = 3.3V, VCCIO = 1.8V (TA = 25°C) (Pull-Up On) 0.0 -5.0 -10.0 -15.0 -20.0 -25.0 -30.0 -35.0 -40.0 0 0.5 INPUT VOLTAGE (V) TPD VS SWITCHING (VCCIRI = 3.3V, VCCIO = 1.5-3.3V 25C) 7.2 7.0 6.8 6.6 6.4 6.2 1.5V 6.0 1.8V 5.8 2.5V 5.6 3.3V 5.4 5.2 5.0 4 SWITCHING ATF1508RE 1.5V 1.8V 2.5V 3.3V 1 1.5 1.8 1.5V 1.8V 2.5V 3.3V 27 ...
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... ATF1508RE-5CX132 7 6.5 ATF1508RE-7CU132 Note: For shaded devices, contact marketing for availability. 100A 100-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 132C1 132-ball, Plastic Chip-Size Ball Grid Array Package (CBGA) ATF1508RE 28 Package 100A 100A 132C1 132C1 Package Type Operation Range Commercial (0° +70° C) Industrial (-40° ...
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... Orchard Parkway San Jose, CA 95131 R 3682A–PLD–10/08 B PIN 1 IDENTIFIER TITLE 100A, 100-lead Body Size, 1.0 mm Body Thickness, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATF1508RE A2 A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – ...
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... Revision History Revision Level – Release Date A – October 2008 ATF1508RE 30 History Initial release 3682A–PLD–10/08 ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Mentor Graphics ® Corporation. Verilog is the registered trademarks of Cadence Design Systems, Inc ...