xcv100-5tqg144i Xilinx Corp., xcv100-5tqg144i Datasheet - Page 39

• Manufacturer Part Number: xcv100-5tqg144i
• Manufacturer: Xilinx Corp.

CLB SelectRAM Switching Characteristics
DS003-3 (v3.2) September 10, 2002
Production Product Specification
Notes:
1.
Sequential Delays
Clock CLK to X/Y outputs (WE active) 16 x 1 mode
Clock CLK to X/Y outputs (WE active) 32 x 1 mode
Shift-Register Mode
Clock CLK to X/Y outputs
Setup and Hold Times before/after Clock CLK
F/G address inputs
BX/BY data inputs (DIN)
CE input (WE)
Shift-Register Mode
BX/BY data inputs (DIN)
CE input (WS)
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Minimum clock period to meet address write cycle
time
Shift-Register Mode
Minimum Pulse Width, High
Minimum Pulse Width, Low
A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
R
Description
(1)
www.xilinx.com
1-800-255-7778
T
T
T
T
T
Symbol
T
T
SHCKO16
SHCKO32
WS
T
SHCECK
T
DS
AS
SHDICK
T
T
T
T
SRPH
SRPL
WPH
REG
WPL
WC
/T
/T
/T
AH
DH
WH
0.25 / 0
0.34 / 0
0.38 / 0
0.34
0.38
Min
Virtex™ 2.5 V Field Programmable Gate Arrays
1.2
1.2
1.2
1.2
1.2
2.4
1.2
1.2
Setup Time / Hold Time
0.5 / 0
0.7 / 0
0.8 / 0
Speed Grade
2.3
2.7
3.7
0.7
0.8
2.4
2.4
4.8
2.4
2.4
-6
0.6 / 0
0.8 / 0
0.9 / 0
2.6
3.1
4.1
0.8
0.9
2.7
2.7
5.4
2.7
2.7
-5
0.7 / 0
0.9 / 0
1.0 / 0
3.0
3.5
4.7
0.9
1.0
3.1
3.1
6.2
3.1
3.1
-4
Module 3 of 4
ns, max
ns, max
ns, max
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
Units
15