at94k05al-25aqi ATMEL Corporation, at94k05al-25aqi Datasheet - Page 56

• Manufacturer Part Number: at94k05al-25aqi
• Description: 5k - 40k Gates Of At40k Fpga With 8-bit Microcontroller, Up To 36k Bytes Of Sram And On-chip Jtag Ice
• Manufacturer: ATMEL Corporation

56
AT94K Series FPSLIC
Figure 33. Out Instruction – AVR Writing to the FPGA
Note:
Figure 34. In Instruction – AVR Reading FPGA
Notes:
(FPGA DATA OUT)
(FISUA, B, C or D)
(FISUA, B, C or D)
SYSTEM CLOCK)
FPGA CLOCK
(FPGA DATA IN)
AVR CLOCK
AVR CLOCK
FPGA IOWE
FPGA IORE
SELECT "n"
AVR IOADR
SELECT "n"
AVR IOADR
AVR DBUS
AVR DBUS
2. At the end of an FPGA read cycle, there is a chance for the AVR data bus contention
1. AVR expects Write to be captured by the FPGA upon posedge of the AVR clock.
1. AVR captures read data upon posedge of the AVR clock.
AVR IOWE
(SET TO AVR
AVR IORE
AVR INST
AVR INST
FPGA I/O
FPGA I/O
between the FPGA and another peripheral to start to drive (active IORE at new address ver-
sus FPGAIORE + Select “n”), but since the AVR clock would have already captured the data
from AVR DBUS (= FPGA Data Out), this is a “don’t care” situation.
OUT INSTRUCTION
IN INSTRUCTION
WRITE DATA VALID
READ DATA VALID
(1)
(2)
(2)
Rev. 1138F–FPSLI–06/02
(1)