ksz8851-mql Micrel Semiconductor, ksz8851-mql Datasheet - Page 8

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ksz8851-mql

Manufacturer Part Number
ksz8851-mql
Description
Single-port Ethernet Mac Controller With 8/16-bit Or 32-bit Non-pci Interface
Manufacturer
Micrel Semiconductor
Datasheet
Micrel, Inc.
KSZ8851-16/32 MQL/MQLI
List of Figures
Figure 1. KSZ8851-16/32MQL/MQLI Functional Diagram ..................................................................................................... 1
Figure 2.128-Pin PQFP for 16-Bit ......................................................................................................................................... 10
Figure 3.128-Pin PQFP for 32-Bit ......................................................................................................................................... 16
Figure 4. Typical Straight Cable Connection ....................................................................................................................... 26
Figure 5. Typical Crossover Cable Connection ................................................................................................................... 27
Figure 6. Auto Negotiation and Parallel Operation .............................................................................................................. 28
Figure 7. KSZ8851M 8-Bit, 16-Bit, and 32-Bit Data Bus Connections ................................................................................ 33
Figure 8. Host TX Single Frame in Manual Enqueue Flow Diagram ................................................................................... 36
Figure 9. Host TX Multiple Frames in Auto- Enqueue Flow Diagram .................................................................................. 37
Figure 10. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram ................................................................. 39
Figure 11. PHY Port 1 Near-end (Remote) and Host Far-end (Local) Loopback Paths ...................................................... 41
Figure 12. Asynchronous Cycle ........................................................................................................................................... 81
Figure 13. Address Latching Cycle for All Modes ................................................................................................................ 82
Figure 14. Auto Negotiation Timing ..................................................................................................................................... 83
Figure 15. Reset Timing ....................................................................................................................................................... 84
Figure 16. EEPROM Read Cycle Timing Diagram .............................................................................................................. 85
Figure 17. 128-Pin PQFP Package ...................................................................................................................................... 87
February 2009
8
M9999-021309-1.1

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