at43101 ATMEL Corporation, at43101 Datasheet - Page 4

• Manufacturer Part Number: at43101
• Description: Pcmcia Card Memory Interface Circuit With 256 Bytes Of Internal Attribute Memory Eeprom
• Manufacturer: ATMEL Corporation

System Block Diagram
Operation
The AT43101 is used in pairs to implement PCMCIA
Release 2.1 compatible memory cards as shown in the sys-
tem block diagram and in the internal chip block diagrams.
Both PCMCIA signals and memory devices connect directly
to the AT43101 with no additional components required. The
AT43101 acts as a data and address buffer and address and
control signal decoder for both an external memory array and
an internal 256x8 E2PROM which contains the Card Infor-
mation Structure.
The memory card is mapped into the Common Memory Ad-
dress Space of PCMCIA according to the address signals
connected to the DEC[2:0], SEL[1:0], and SGL/DBL* inputs.
In a typical configuration, SGL/DBL* and SEL[1:0] are tied
high or left floating since they are pulled up internally. Then
DEC[2:0] function as direct inputs to the address/chip enable
decoder.
For example, A[25:23] are connected to DEC[2:0] and
IA[22:1] are connected to A[21:0] of sixteen 4 Mbyte devices.
Note that A0 is used in conjunction with CE1* and CE2* to
4
SGL/DBL*
DEC[2:0]
SEL[1:0]
RESET
RESET
A[24:9]
D[15:0]
REG*
REG*
CE1*
CE1*
CE2*
A[8:0]
CE2*
WE*
OE*
OE*
WE*
A0
R/B*
WP
AT43101"A"
AT43101"B"
AT43101
IA[24:9]
IA[8:1]
WPATT
IR/B*
IR*
IWP*
IOEH*
IWEL*
IWEH*
IOEL*
OE* CE* WE*
OE* CE* WE*
MEMORY DEVICE
MEMORY DEVICE
INTERNAL DATA BUS: ID[15:0]
DATA
DATA
decode the data access and is not used as a common
memory address. A[25:23] then determine which ICE[7:0]
line is active.
Mixed memory size applications can use SGL/DBL* pulled
low to enable a mixed mode decoding. This then enables
either DEC[2:0] or SEL[1:0] as inputs to the address/chip
enable decoder based on the state of SEL[1:0].
For example, the common memory space contains eight
1 Mbyte SRAM devices and six 4 Mbyte Flash devices.
A[22:21] are connected to DEC[1:0] (DEC[2] is a don’t care)
and A[24:23] are connected to SEL[1:0]. Then IA[22:1] are
used to connect to A[19:0] of the SRAM and A[21:0] of the
Flash devices. ICE[3:0]* are connected to the four SRAM
banks and ICE[7:5] to the three Flash banks. The SRAM is
then memory mapped to the lower 4 M words of addressing
and the Flash to the next 12 M words. All addressing is con-
tiguous. Notice that ICE4* can not be used with this decoding
scheme.
ICE[7:0]*
OE* CE* WE*
MEMORY DEVICE
OE* CE* WE*
MEMORY DEVICE
DATA
DATA
OE* CE* WE*
OE* CE* WE*
MEMORY DEVICE
MEMORY DEVICE
DATA
DATA