mc68hc908jg16 Freescale Semiconductor, Inc, mc68hc908jg16 Datasheet - Page 7
mc68hc908jg16
Manufacturer Part Number
mc68hc908jg16
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC908JG16.pdf
(324 pages)
- Current page: 7 of 324
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MC68HC908JG16
MOTOROLA
Technical Data — MC68HC908JG16
—
Rev. 1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
1.6.6
1.6.7
1.6.8
1.6.9
1.6.10
1.6.11
1.6.12
2.1
2.2
2.3
Freescale Semiconductor, Inc.
For More Information On This Product,
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 39
Power Supply Pins (V
Voltage Regulator Output Pin (V
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . 35
External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
External Interrupt Pins (IRQ, PTE4/D–) . . . . . . . . . . . . . . . .35
Analog Power Supply Pins (V
Analog Voltage Regulator Out (V
Port A Input/Output (I/O) Pins
Port B I/O Pins (PTB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Port C I/O Pins (PTC1/RxD, PTC0/TxD) . . . . . . . . . . . . . . . 36
Port D I/O Pins (PTD3–PTD0) . . . . . . . . . . . . . . . . . . . . . . . 36
Port E I/O Pins (PTE4/D–, PTE3/D+, PTE2/T2CH01,
Go to: www.freescale.com
(PTA7/KBA7/AD7–PTA0/KBA0/AD0) . . . . . . . . . . . . . . . 36
PTE1/T1CH01, PTE0/TCLK). . . . . . . . . . . . . . . . . . . . . . 36
Table of Contents
Section 1. General Description
Section 2. Memory Map
DD
, V
SS
DDA
) . . . . . . . . . . . . . . . . . . . . . . .33
Table of Contents
REG
REGA
, V
SSA
). . . . . . . . . . . . . . . . . . 34
) . . . . . . . . . . . . . . . . 35
) . . . . . . . . . . . . . . . 35
Technical Data
7
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