mc68hc901fn Freescale Semiconductor, Inc, mc68hc901fn Datasheet
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mc68hc901fn Summary of contents
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MC68HC901 Multi-Function Peripheral Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability ...
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Trademarks: Motorola and the Motorola symbol are registered trademark(s) of Motorola, Inc. ii MC68HC901 USER’S MANUAL MOTOROLA ...
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Documentation Comments FAX 512-891-8593—Documentation Comments Only The Motorola High-Performance Embedded Systems Technical Communications Department provides a fax number for you to submit any questions or comments about this document or how to order other documents. We welcome your suggestions for ...
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Applications and Technical Information For questions or comments pertaining to technical information, questions, and applications, please contact one of the following sales offices nearest you. Field Applications Engineering Available Through All Sales Offices UNITED STATES ALABAMA , Huntsville ARIZONA , ...
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The complete documentation package for the MC68HC901 consists of the MC68HC901UM/ AD and the M68000 Family Programmer’s Reference Manual , which contains the complete instruction set for the M68000 Family. The MC68HC901 Multi-Function Peripheral User’s Manual describes the programming, capabilities, ...
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TABLE OF CONTENTS Paragraph Number 1.1 Key Features .............................................................................................1-2 1.2 Register Programming ...............................................................................1-2 2.1 Power Supply (V 2.2 Clock (CLK) .............................................................................................. 2-2 2.3 Data Bus (D7–D0) .................................................................................... 2-2 2.4 Asynchronous Bus Control ....................................................................... 2-2 2.4.1 Chip Select (CS) .................................................................................. 2-2 ...
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TABLE OF CONTENTS (Continued) Paragraph Number 3.1 Data Transfer Operations ......................................................................... 3-1 3.1.1 Read Cycle .......................................................................................... 3-1 3.1.2 Write Cycle .......................................................................................... 3-2 3.2 Interrupt Acknowledge Operation ............................................................. 3-2 3.3 Reset Operation ....................................................................................... 3-3 4.1 Interrupt Processing ................................................................................. 4-1 4.1.1 Interrupt ...
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TABLE OF CONTENTS (Continued) Paragraph Number 6.2.1 Timer Data Registers (TxDR) .............................................................. 6-4 6.2.2 Timer Control Registers (TxCR) .......................................................... 6-4 Universal Synchronous/Asynchronous Receiver-Transmitter 7.1 Character Protocols .................................................................................. 7-1 7.1.1 Asynchronous Format ......................................................................... 7-2 7.1.2 Synchronous Format ........................................................................... 7-2 7.1.3 USART ...
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LIST OF ILLUSTRATIONS Figure Number 1-1. MFP Block Diagram ........................................................................................ 1-1 2-1. Input and Output Signals ................................................................................ 2-1 3-1. Read Cycle Timing Diagram ........................................................................... 3-2 3-2. Write Cycle Timing Diagram ........................................................................... 3-2 3-3. IACK Cycle Timing Diagram ........................................................................... 3-3 4-1. ...
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Table Number 1-1. MFP Register Map ......................................................................................... 1-2 2-1. Signal Summary ............................................................................................. 2-5 MOTOROLA LIST OF TABLES Title MC68HC901 USER’S MANUAL Page Number xiii ...
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SECTION 1 INTRODUCTION The MC68HC901 Multi-Function Peripheral (MFP member of the M68000 Family of peripherals. Unless otherwise specified, the MC68HC901 multi-function peripheral is hereafter referred to as the MFP in this document. Many features of the MFP make ...
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Introduction 1.1 KEY FEATURES The MFP performs many of the functions common to most microprocessor-based systems. The resources available to the user include: • Eight individually programmable I/O pins with interrupt capability • 16-source interrupt controller with individual source enable ...
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Table 1-1. MFP Register Map (Continued) ADDRESS HEX BINARY RS5 RS4 RS3 RS2 ...
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SECTION 2 SIGNAL DESCRIPTION This section contains descriptions of the input and output signals. The input and output signals can be functionally organized into groups as shown in Figure 2-1. The following paragraphs provide a brief description of the signal ...
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Signal Description 2.2 CLOCK (CLK) The clock input is a single-phase TTL-compatible signal used for internal timing. This input must conform to minimum pulse width times. The clock is not necessarily the system clock in frequency or phase. 2.3 DATA ...
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INTERRUPT CONTROL The interrupt request and interrupt acknowledge signals are handshake lines for a vectored interrupt scheme. Interrupt enable in and interrupt enable out implement a daisy-chained interrupt structure. 2.7.1 Interrupt Request (IRQ) This active low, open-drain output signals ...
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Signal Description 2.9 TIMER CONTROL These lines provide internal timing and auxiliary timer control inputs required for certain operating modes. Additionally, the timer outputs are included in this group. 2.9.1 Timer Inputs (TAI and TBI) These input lines are control ...
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Signal Description 2.10.2 Serial Output (SO) This output line is the USART transmitter data output. This output high-impedance state after a device reset. 2.10.3 Receiver Clock (RC) This input controls the serial bit rate of the receiver. ...
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Signal Description Table 2-1. Signal Summary (Continued) SIGNAL NAME Data Transfer Acknowledge Register Select Bus Data Bus Reset Interrupt Request Interrupt Acknowledge Interrupt Enable In Interrupt Enable Out General Purpose Timer Clock Timer Inputs Timer Outputs Serial ...
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SECTION 3 BUS OPERATION The following paragraphs describe control signals and the bus operation during data transfer, interrupt acknowledge, and reset operations. 3.1 DATA TRANSFER OPERATIONS Transfer of data between devices involves the following pins: • Register Select Bus – ...
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Bus Operation CLK RS1 - RS5 DTACK Figure 3-1. Read Cycle Timing Diagram 3.1.2 Write Cycle To write a register, CS and DS must be asserted, and R/W must be low. The ...
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When the MFP asserts DTACK to indicate that valid data is on the bus, the processor will latch the data and terminate the bus cycle by negating DS. When either DS or IACK is negated, the MFP will terminate the ...
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Bus Operation I/O lines are placed in the high-impedance input mode, and the timer outputs are driven low. External MFP signals are negated. Since the vector register (VR) is initialized to a $00, an uninitialized MFP may not respond to ...
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SECTION 4 INTERRUPT STRUCTURE In an M68000 system, the MFP will be assigned to one of the seven possible interrupt levels. All interrupt service requests from the MFP 16 interrupt channels will be presented at this level interrupt ...
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Interrupt Structure IV3-IV0 — Interrupt Vector These bits are supplied by the MFP. They are the binary channel number of the highest priority channel that is requesting interrupt service. IV3 IV2 ...
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V7-V4 — Vector These upper four bits of the vector register are written by the user. These bits become the most-significant four bits of the interrupt vector number. S — In-Service Register Enable 1 = Software end-of-interrupt mode and in-service ...
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Interrupt Structure 4.3 INTERRUPT CONTROL REGISTERS MFP interrupt processing is managed by the enable registers A and B, interrupt pending registers A and B, and interrupt mask registers A and B. These registers allow the programmer to enable or disable ...
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Interrupt Structure Receiver Error — Receiver Buffer Full Interrupt Enable 1 = Enable Disable. Transmitter Buffer Empty — Transmitter Buffer Interrupt Enable 1 = Enable Disable. Transmitter Error — Transmitter Error Interrupt Enable 1 = Enable. ...
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Interrupt Structure 4.3.2 Interrupt Pending Registers (IPRA, IPRB) When an interrupt is received on an enabled channel, the corresponding interrupt pending bit is set in interrupt pending register (IPRA or IPRB vectored interrupt scheme, this ...
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Interrupt Structure IPRB REGISTER BIT 7 6 FIELD GPIP5 GPIP4 RESET 0 0 ADDR GPIP5-GPIP4 — General Purpose Interrupt Pending 1 = Pending Cleared. Timer C — Timer C Interrupt Pending 1 = Pending Cleared. Timer ...
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Interrupt Structure 4.3.3 Interrupt Mask Registers (IMRA, IMRB) Interrupts are masked for a channel by clearing the appropriate bit in interrupt mask register (IMRA or IMRB). Even though an enabled channel is masked, the channel will recognize ...
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Interrupt Structure Timer B — Timer B Interrupt Mask 1 = Unmask Mask. IMRB REGISTER BIT 7 6 FIELD GPIP5 GPIP4 RESET 0 0 ADDR GPIP5-GPIP4 — General Purpose Interrupt Mask 1 = Unmask Mask. Timer ...
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Interrupt Structure 4.3.4 Interrupt In-Service Registers (ISRA, ISRB) These registers indicate whether interrupt processing is in progress for a certain channel. A bit is set whenever an interrupt vector number is passed for a interrupt channel during an IACK cycle ...
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Interrupt Structure ISRB REGISTER BIT 7 6 FIELD GPIP5 GPIP4 RESET 0 0 ADDR GPIP5-GPIP4 — General Purpose Interrupt Servicing 1 = In-service service in progress. Timer C — Timer C Interrupt Servicing 1 = In-service. 0 ...
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Interrupt Structure the MFP is placed in the software end-of-interrupt mode, and when the S bit is a zero, all channels operate in the automatic end-of-interrupt mode. 4.4.2 Automatic End-Of-Interrupt Mode When an interrupt vector is passed to the processor ...
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SECTION 5 GENERAL PURPOSE INPUT/OUTPUT PORT The general purpose input/output (I/O) port (GPIP) provides eight I/O lines (I0 through I7) that may be operated as either inputs or outputs under software control. In addition, these lines may optionally generate an ...
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General Purpose Input/Output Port the active edge register will cause the associated input to generate an interrupt on the one- to-zero transition. Writing a one to the edge bit will produce an interrupt on the zero-to-one transition of the corresponding ...
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SECTION 6 TIMERS The MFP contains four 8-bit timers which provide many functions typically required in microprocessor systems. The timers can supply the baud rate clocks for the on-chip serial I/O channel, generate periodic interrupts, measure elapsed time, and count ...
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Timers If the main counter is loaded with 01 (hexadecimal), a time out pulse will occur every time the prescaler presents a count pulse to the main counter. If the main counter is loaded with 00, a time out pulse ...
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The state of the active edge bit also specifies whether a zero-to-one transition or a one-to- zero transition of the auxiliary input pin will produce an interrupt when the interrupt channel is enabled. In normal operation, programming the active edge ...
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Timers The active edge of the auxiliary input signal is defined by the associated channel's edge bit. GPIP4 of the AER specifies the active edge for TAI, and GPIP3 defines the active edge for TBI. When the edge bit is ...
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Timers TACR REGISTER BIT 7 6 FIELD * * RESET 0 0 ADDR TBCR REGISTER BIT 7 6 FIELD * * RESET 0 0 ADDR Bits 7-5 — *Unused Unused bits read as zero. Reset TAO/TBO — Reset Timer A ...
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Timers AC3 AC2 BC3 BC2 TCDCR REGISTER BIT 7 6 FIELD * CC2 RESET 0 0 ADDR Bit 7, Bit 3 — *Unused Unused bits read ...
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SECTION 7 UNIVERSAL SYNCHRONOUS/ASYNCHRONOUS RECEIVER-TRANSMITTER The universal synchronous asynchronous receiver-transmitter (USART single, full- duplex serial channel with a double-buffered receiver and transmitter. There are separate receive and transmit clocks and, also, separate receive and transmit status and data ...
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Universal Synchronous/Asynchronous Receiver-Transmitter 7.1.1 Asynchronous Format Variable character length and start/stop bit configurations are available under software control for asynchronous operation. The user can choose a character length from five to eight bits and a stop bit length of one, ...
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USART Control Register (UCR) This register selects the clock mode and the character format for the receive and transmit sections. UCR REGISTER BIT 7 6 FIELD CLK CL1 RESET 0 0 ADDR CLK — Clock Mode 1 = Data ...
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Universal Synchronous/Asynchronous Receiver-Transmitter PE — Parity Enable 1 = Parity checked by receiver and parity calculated and inserted during data transmission parity check and no parity bit computed for transmission. E/O — Even/Odd Parity 1 = Even ...
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Universal Synchronous/Asynchronous Receiver-Transmitter the RSR was read to access the status information for the first data word, the flags for the new word would be retrieved. 7.2.1 Receiver Interrupt Channels The USART receiver section is assigned two interrupt channels. One ...
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Universal Synchronous/Asynchronous Receiver-Transmitter 1 = Receiver buffer full and incoming word received Read by RSR. PE— Parity Error 1 = Parity error detected on character transfer to receiver buffer parity error detected on character transfer ...
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Universal Synchronous/Asynchronous Receiver-Transmitter RE — Receiver Enable This bit should not be set until the receiver clock is active. When the transmitter is disabled in auto-turnaround mode this bit is set Receiver operation is enabled Receiver ...
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Universal Synchronous/Asynchronous Receiver-Transmitter In the asynchronous character format, the transmitter can be programmed to send a break. The break will be transmitted once the word currently in the shift register has been sent. If the shift register is empty, the ...
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Universal Synchronous/Asynchronous Receiver-Transmitter 1 = Character in the TSR was transmitted before a new word was loaded into the transmit buffer Transmitter disabled or read performed on TSR. AT — Auto-Turnaround When set, the receiver will be enabled ...
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Universal Synchronous/Asynchronous Receiver-Transmitter interrupts for this channel. Once the transfer is complete, interrupt pending register A is read. Any pending receiver or transmitter error indicates an error in the data transfer asserted when the buffer full bit is ...
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SECTION 8 ELECTRICAL CHARACTERISTICS This section contains the electrical specifications and associated timing information for the MC68HC901 multi-function peripheral. Refer to Section 9 Ordering Information and Mechanical Data for specific part numbers corresponding to voltage, frequency, and temperature rating. 8.1 ...
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Electrical Characteristics 8.3 POWER CONSIDERATIONS The average chip-junction temperature • ...
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DC ELECTRICAL CHARACTERISTICS ( ˚ ˚ CHARACTERISTIC Input High Voltage, except XTAL1 Input Low Voltage, except XTAL1 XTAL1 Input High Voltage XTAL1 Input Low Voltage Output High Voltage, Except IRQ, DTACK (I ...
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Electrical Characteristics 8.6 CLOCK TIMING (See Figure 8-1) NUM CHARACTERISTIC — Frequency of Operation 1 Cycle Time 2, 3 Clock Pulse Width 4, 5 Rise and Fall Times 2 Figure 8-1. Clock Input Timing Diagram 10 ...
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Electrical Characteristics 8.7 AC ELECTRICAL CHARACTERISTICS (V = 5.0 Vdc 5%; GND = 0 Vdc Figures 8-3 through 8-12) NUM CHARACTERISTIC 4 CS, DS Width High 1 2 R/W, RS1-RS5 Valid to Falling CS Setup Time 3 Data ...
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Electrical Characteristics NUM CHARACTERISTIC 28 Receiver Ready (RR) Delay from Rising RC 29 Transmitter Ready (TR) Delay from Rising TC 30 TxO ( Low from Rising Edge (Reset Time) 3 Timer Output (TxO) Valid ...
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Electrical Characteristics 8.8 TIMER AC CHARACTERISTICS Definitions: Error = Indicated time value – actual time value Prescale Value psc CLK Internal Timer Mode: Single Interval Error (Free Running) (See Note 2 below ...
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Electrical Characteristics 23 CLK RS1 - RS5 DTACK CLK RS1 - RS5 DTACK 8 Figure 8-3. ...
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Electrical Characteristics CLK IACK DS IEI IEO DTACK NOTE: IEO only goes low if no acknowledgeable interrupt is pending. If IEO goes low, DTACK and the data bus remain in the high-impendance state. Figure 8-5. Interrupt Acknowledge ...
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Electrical Characteristics CLK 4 IACK DS IEI IEO DTACK NOTES: 1. IEO only goes low if no acknowledgable interrupt is pending. If IEO goes low, DTACK and the data bus remain in the high-impedance state. 2. DTACK ...
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Electrical Characteristics RESET IRQ (BUFFER FULL CONDITION) IRQ (ERROR CONDITION) (DIVIDE-BY-1 MODE ONLY (DIVIDE-BY-16-MODE) SO (DIVIDE-BY-1-MODE) IRQ 8-11 35 Figure 8-9. Reset Timing Figure 8-10. Receiver ...
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Electrical Characteristics XTAL1 / XTAL2 IACK INTERNAL TIMEOUT TAO / TBO / TCO / TDO NOTE: Specification # 30 applies to timer outputs TAO and TBO only. 8- Figure 8-12. Timer ...
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SECTION 9 MECHANICAL DATA AND ORDERING INFORMATION This section contains the pin assignments, package dimensions, and ordering information for the MC68HC901 multi-function peripheral. 9.1 PIN ASSIGNMENTS PACKAGE 48-Pin Dual-In-Line (Plastic) 52-Lead QUAD Figure 9-1. 48-Pin Dual-In-Line Package (Plastic) MOTOROLA MC68HC901 ...
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Mechanical Data and Ordering Information TAO TBO TCO TDO XTAL1 XTAL2 Figure 9-2. 52-Lead QUAD Package 9.2 PACKAGE DIMENSIONS CASE PACKAGE 48-Pin Dual-In-Line (Plastic) 52-Lead QUAD - -T- SEATING PLANE ...
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(NOTE (NOTE 1) DETAIL 0.25 (0.010 ...
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... Mechanical Data and Ordering Information 9.3 ORDERING INFORMATION PACKAGE TYPE MAXIMUM CLOCK Plastic P Suffix 4.0 MHz Quad Pack FN Suffix 4.0 MHz 9-4 TEMPERATURE RANGE FREQUENCY 0 ˚ ˚C 0 ˚ ˚C MC68HC901 USER’S MANUAL ORDER NUMBER MC68HC901P MC68HC901FN MOTOROLA ...
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Numerics 48-Pin Dual-In-Line Package (Plastic) ..................................... 9-1 52-Lead QUAD Package ..................... 9 Electrical Characteristics ............... 8-5 Active Edge Register (AER) ................ 5-1 AER register ........................................ 5-2 Asynchronous Bus Control .................. 2-2 Asynchronous Format .......................... 7-2 Automatic End-Of-Interrupt Mode ...
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Index GPIP Registers Active Edge Register (AER) ........... 5-2 Data Direction Register (DDR) ....... 5-2 General Purpose I/O Data Register (GPDR) ................. 5-1 I IACK Cycle Timing Diagram ................ 3-3 IERA register ....................................... 4-4 IERB register ....................................... 4-5 IMRA register ...
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Receiver Timing ................................. 8-11 register programming ........................... 1-2 Register Select Bus Signals ................ 2-2 Reset Operation ................................... 3-3 Reset Signal ........................................ 2-2 Reset Timing ...................................... 8-11 RSR register ........................................ 7-5 S SCR register ........................................ 7-2 Section(s) Bus Operation ................................ 3-1 ...
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Index VR register ........................................... 4-2 W Write Cycle Timing .............................. 8-8 Write Cycle Timing Diagram ................ 3-2 INDEX-4 MC68HC901 USER’S MANUAL MOTOROLA ...