mc68hc912bc32 Freescale Semiconductor, Inc, mc68hc912bc32 Datasheet - Page 31

• Manufacturer Part Number: mc68hc912bc32
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
1. The RxCAN and TxCAN designations are for the MC68HC(9)12BC32 only.
ADDR15–ADDR8
DLCRx/RxCAN
DLCTx/TxCAN
ADDR7–ADDR0
DATA15–DATA8
IPIPE1, IPIPE0
MODB, MODA
DATA7–DATA0
IOC7–IOC0
SDO/MOSI
PW3–PW0
AN7–AN0
SDI/MISO
RESET
LSTRB
TAGLO
EXTAL
CS/SS
BKGD
TAGHI
Name
ECLK
XIRQ
RxD0
XTAL
TxD0
DBE
SCK
R/W
IRQ
Pin
PAI
(1)
(1)
16–12, 9–7
Number
25–18
46–39
58–51
27, 28
27, 28
3–6
Pin
16
26
29
32
33
34
35
35
36
37
38
17
17
76
75
68
67
66
65
62
61
Table 1-3. Signal Description Summary
Pulse-width modulator channel outputs
External bus pins share function with general-purpose I/O ports A and B. In single-chip
modes, the pins can be used for I/O. In expanded modes, the pins are used for the
external buses.
Pins used for input capture and output compare in the timer and pulse accumulator
subsystem
Pulse accumulator input
Analog inputs for the analog-to-digital conversion module
Data bus control and, in expanded mode, enables the drive control of external buses
during external reads
State of mode select pins during reset determines the initial operating mode of the
MCU. After reset, MODB and MODA can be configured as instruction queue tracking
signals IPIPE1 and IPIPE0 or as general-purpose I/O pins.
E-clock is the output connection for the external bus clock. ECLK is used as a timing
reference and for address demultiplexing.
An active low bidirectional control signal, RESET acts as an input to initialize the MCU
to a known startup state and an output when COP or clock monitor causes a reset.
Crystal driver and external clock input pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
Low byte strobe (0 = low byte valid), in all modes this pin can be used as I/O. The low
strobe function is the exclusive-NOR of A0 and the internal SZ8 signal. The SZ8
internal signal indicates the size 16/8 access.
Pin used in instruction tagging
Indicates direction of data on expansion bus; shares function with general-purpose I/O;
read/write in expanded modes
Maskable interrupt request input provides a means of applying asynchronous interrupt
requests to the MCU. Either falling edge-sensitive triggering or level-sensitive
triggering is program selectable (INTCR register).
Provides a means of requesting asynchronous non-maskable interrupt requests after
reset initialization
Single-wire background interface pin is dedicated to the background debug function.
During reset, this pin determines special or normal operating mode.
Pin used in instruction tagging
BDLC receive pin
BDLC transmit pin
Slave-select output for SPI master mode; input for slave mode or master mode
Serial clock for SPI system
Master out/slave in pin for serial peripheral interface
Master in/slave out pin for serial peripheral interface
SCI transmit pin
SCI receive pin
M68HC12B Family Data Sheet, Rev. 9.1
Description
Pinout and Signal Descriptions
31