mc68hc912bl16 Freescale Semiconductor, Inc, mc68hc912bl16 Datasheet - Page 80

• Manufacturer Part Number: mc68hc912bl16
• Description: 16-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

TQCR — Reserved
TCTL1 — Timer Control Register 1
TCTL2 — Timer Control Register 2
OMn — Output Mode
OLn — Output Level
TCTL3 — Timer Control Register 3
80
RESET:
RESET:
RESET:
RESET:
Read or write anytime.
These eight pairs of control bits are encoded to specify the output action to be taken as a result of a
successful OCn compare. When either OMn or OLn is one, the pin associated with OCn becomes an
output tied to OCn regardless of the state of the associated DDRT bit.
1 = For TFLG1($8E), a read from an input capture or a write to the output compare channel ($90–
$9F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 ($8F), any access
to the TCNT register ($84, $85) clears the TOF flag. Any access to the PACNT register ($A2,
$A3) clears the PAOVF and PAIF flags in the PAFLG register ($A1). This has the advantage of
eliminating software overhead in a separate clear sequence. Extra care is required to avoid ac-
cidental flag clearing due to unintended accesses.
EDG7B
OM7
OM3
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
0
0
Port T[6] is not bonded to any pin in MC68HC912BL16.
EDG7A
OL7
OL3
OMn
6
0
0
6
0
6
0
6
0
0
0
1
1
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 25 Compare Result Output Action
EDG6B
OM6
OM2
5
0
0
5
0
5
0
5
0
OLn
0
1
0
1
Go to: www.freescale.com
EDG6A
OL6
OL2
Timer disconnected from output pin logic
4
0
0
4
0
4
0
4
0
NOTE
Clear OCn output line to zero
Set OCn output line to one
Toggle OCn output line
EDG5B
OM5
OM1
3
0
0
3
0
3
0
3
0
Action
EDG5A
OL5
OL1
2
0
0
2
0
2
0
2
0
EDG4B
OM4
OM0
1
0
0
1
0
1
0
1
0
MC68HC912BL16TS/D
EDG4A
MC68HC912BL16
Bit 0
Bit 0
Bit 0
Bit 0
OL4
OL0
0
0
0
0
0
$008A
$0087
$0088
$0089